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ld-cdwhitequark
ld-cd
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whitequark
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Fix Alchtiry PTV2 formatting
Whoopsie format on save was still on on my desktop
1 parent ea44949 commit 96dfc33

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Lines changed: 42 additions & 73 deletions

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‎amaranth_boards/alchitry_ptv2.py‎

Lines changed: 42 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
from amaranth.vendor import XilinxPlatform
77
from .resources import *
88

9+
910
__all__ = ["AlchitryPtV2Platform", "AlchitryPtV2AlphaPlatform"]
1011

1112

@@ -22,76 +23,69 @@ def find_loader():
2223

2324
alpha_top_connectors = [
2425
Connector(
25-
"alchitry_a",
26-
0,
26+
"alchitry_a", 0,
2727
"- - AB22 AB18 AB21 AA18 - - E3 N2 F3 P2 - - M2 L1 M3 M1 - - "
2828
"J6 D2 K6 E2 - - M5 L4 M6 L5 - - P4 N5 P5 P6 - - G4 G3 "
2929
"H4 H3 - - J4 K3 K4 L3 - - P1 N3 R1 N4 - - B2 A1 C2 B1 "
30-
"- - F1 D1 G1 E1 - - H5 G2 J5 H2 - - J1 J2 K1 K2 - - ",
30+
"- - F1 D1 G1 E1 - - H5 G2 J5 H2 - - J1 J2 K1 K2 - - "
3131
),
3232
Connector(
33-
"alchitry_b",
34-
0,
33+
"alchitry_b", 0,
3534
"- - AB13 AA11 AA13 AA10 - - AB12 Y14 AB11 W14 - - AB15 W16 AA15 W15 - - "
3635
"AB17 V19 AB16 V18 - - Y19 V20 Y18 U20 - - AB10 W10 AA9 V10 - - W12 Y12 "
3736
"W11 Y11 - - V14 V15 V13 U15 - - AB20 AA16 AA19 Y16 - - W17 T15 V17 T14 "
38-
"- - AA14 R16 Y13 P15 - - R17 T18 P16 R18 - - N14 P17 N13 N17 - - ",
37+
"- - AA14 R16 Y13 P15 - - R17 T18 P16 R18 - - N14 P17 N13 N17 - - "
3938
),
4039
Connector(
41-
"alchitry_c",
42-
0,
40+
"alchitry_c", 0,
4341
"- - - - - - - - - - - - - - - - - - - - "
44-
"- - - - - - - - U18 Y1 U17 W1 V2 R14 U2 P14 - - - - ",
42+
"- - - - - - - - U18 Y1 U17 W1 V2 R14 U2 P14 - - - - "
4543
),
4644
]
4745

46+
4847
top_connectors = [
4948
Connector(
50-
"alchitry_a",
51-
0,
49+
"alchitry_a", 0,
5250
"- - AB22 AB18 AB21 AA18 - - E3 N2 F3 P2 - - M2 L1 M3 M1 - - "
5351
"J6 D2 K6 E2 - - M5 L4 M6 L5 - - P4 N5 P5 P6 - - G4 G3 "
5452
"H4 H3 - - J4 K3 K4 L3 - - P1 N3 R1 N4 - - B2 A1 C2 B1 "
55-
"- - F1 D1 G1 E1 - - H5 G2 J5 H2 - - J1 J2 K1 K2 - - ",
53+
"- - F1 D1 G1 E1 - - H5 G2 J5 H2 - - J1 J2 K1 K2 - - "
5654
),
5755
Connector(
58-
"alchitry_b",
59-
0,
56+
"alchitry_b", 0,
6057
"- - R14 R16 P14 P15 - - R17 P17 P16 N17 - - W17 T18 V17 R18 - - "
6158
"AB20 V19 AA19 V18 - - Y19 V20 Y18 U20 - - AB10 AB15 AA9 AA15 - - W12 Y12 "
6259
"W11 Y11 - - V14 V15 V13 U15 - - W10 AB17 V10 AB16 - - AB12 AA16 AB11 Y16 "
63-
"- - AA11 T15 AA10 T14 - - AB13 Y14 AA13 W14 - - AA14 W16 Y13 W15 - - ",
60+
"- - AA11 T15 AA10 T14 - - AB13 Y14 AA13 W14 - - AA14 W16 Y13 W15 - - "
6461
),
6562
Connector(
66-
"alchitry_c",
67-
0,
63+
"alchitry_c", 0,
6864
"- - - - - - - - - - - - - - - - - - - - "
69-
"- - - - - - - - U18 Y1 U17 W1 V2 N14 U2 N13 - - - - ",
65+
"- - - - - - - - U18 Y1 U17 W1 V2 N14 U2 N13 - - - - "
7066
),
7167
]
7268

69+
7370
bottom_connectors = [
7471
Connector(
75-
"alchitry_a",
76-
1,
72+
"alchitry_a", 1,
7773
"- - AB13 AA11 AA13 AA10 - - AB12 Y14 AB11 W14 - - AB15 W16 AA15 W15 - - "
7874
"AB17 V19 AB16 V18 - - Y19 V20 Y18 U20 - - AB10 W10 AA9 V10 - - W12 Y12 "
7975
"W11 Y11 - - V14 V15 V13 U15 - - AB20 AA16 AA19 Y16 - - W17 T15 V17 T14 "
80-
"- - AA14 R16 Y13 P15 - - R17 T18 P16 R18 - - N14 P17 N13 N17 - - ",
76+
"- - AA14 R16 Y13 P15 - - R17 T18 P16 R18 - - N14 P17 N13 N17 - - "
8177
),
8278
Connector(
83-
"alchitry_b",
84-
1,
79+
"alchitry_b", 1,
8580
"- - Y2 AB6 W2 AB7 - - Y7 AB8 Y8 AA8 - - AA6 AB5 Y6 AA5 - - "
8681
"AB2 Y9 AB3 W9 - - T6 W7 R6 V7 - - V8 V5 V9 U6 - - W4 AA4 "
8782
"V4 Y4 - - T4 U5 R4 T5 - - E10 E6 F10 F6 - - C7 C11 D7 D11 "
88-
"- - A6 A10 B6 B10 - - C5 C9 D5 D9 - - A4 A8 B4 B8 - - ",
83+
"- - A6 A10 B6 B10 - - C5 C9 D5 D9 - - A4 A8 B4 B8 - - "
8984
),
9085
Connector(
91-
"alchitry_c",
92-
1,
86+
"alchitry_c", 1,
9387
"- - - - - - - - - - - - - - - - - - - - "
94-
"- - - - - - - - U1 W5 T1 W6 R2 V3 R3 U3 - - - - ",
88+
"- - - - - - - - U1 W5 T1 W6 R2 V3 R3 U3 - - - - "
9589
),
9690
]
9791

@@ -105,62 +99,44 @@ class AlchitryPtV2Platform(XilinxPlatform):
10599

106100
resources = [
107101
Resource(
108-
"clk100",
109-
0,
110-
Pins("W19", dir="i"),
111-
Clock(100e6),
112-
Attrs(IOSTANDARD="LVCMOS33"),
102+
"clk100", 0, Pins("W19", dir="i"),
103+
Clock(100e6), Attrs(IOSTANDARD="LVCMOS33"),
113104
),
114105
Resource("rst", 0, PinsN("N15", dir="i"), Attrs(IOSTANDARD="LVCMOS33")),
106+
115107
# Connected to the onboard FT2232HQ (This and the FIFO are mutually exclusive)
116108
UARTResource(0, rx="AA20", tx="AA21", attrs=Attrs(IOSTANDARD="LVCMOS33")),
117109
# Connected to the onboard FT2232HQ (This and the UART are mutually exclusive)
118-
Resource(
119-
"ftdi_fifo_async",
120-
0,
110+
Resource("ftdi_fifo_async", 0,
121111
Subsignal("d", Pins("AA20 AA21 W21 W22 Y21 Y22 F15 U7", dir="io")),
122112
Subsignal("rxf", PinsN("F21", dir="i")),
123113
Subsignal("txe", PinsN("T3", dir="i")),
124114
Subsignal("rd", PinsN("T16", dir="o")),
125115
Subsignal("wr", PinsN("U16", dir="o")),
126116
Subsignal("siwu", Pins("U16", dir="o")),
127-
Attrs(IO_STANDARD="LVCMOS33"),
117+
Attrs(IO_STANDARD="LVCMOS33")
128118
),
119+
129120
# Connected to the onboard LED array
130121
*LEDResources(pins="P19 P20 T21 R19 V22 U21 T20 W20", attrs=Attrs(IOSTANDARD="LVCMOS33")),
131122
# NOTE: This is also the config flash so don't blow it away
132-
*SPIFlashResources(
133-
0,
134-
cs_n="T19",
135-
clk="L12",
136-
copi="P22",
137-
cipo="R22",
138-
wp_n="P21",
139-
hold_n="R21",
123+
*SPIFlashResources(0,
124+
cs_n="T19", clk="L12", copi="P22", cipo="R22", wp_n="P21", hold_n="R21",
140125
attrs=Attrs(IO_STANDARD="LVCMOS33"),
141126
),
142127
# Connected to the QWIIC connector, not called out in the official pinout
143128
I2CResource(0, scl="F4", sda="L6", attrs=Attrs(IO_STANDARD="LVCMOS33")),
129+
144130
# TODO: Currently untested
145-
DDR3Resource(
146-
0,
147-
rst_n="J19",
148-
clk_p="K17",
149-
clk_n="J17",
150-
clk_en="M22",
151-
cs_n="N16",
152-
we_n="L19",
153-
ras_n="L20",
154-
cas_n="N22",
131+
DDR3Resource(0,
132+
rst_n="J19", clk_p="K17", clk_n="J17", clk_en="M22", cs_n="N16", we_n="L19", ras_n="L20", cas_n="N22",
155133
a="K14 M15 N18 K16 L14 K18 M13 L18 L13 M18 K13 L15 M16 L16",
156134
ba="K19 N20 M20",
157-
dqs_p="K21 J14",
158-
dqs_n="K22 H14",
135+
dqs_p="K21 J14", dqs_n="K22 H14",
159136
dq="J22 M21 L21 J20 H20 G20 J21 H19 H13 G18 J15 H17 G15 G17 G16 H15",
160-
dm="H22 G13",
161-
odt="M17",
137+
dm="H22 G13", odt="M17",
162138
diff_attrs=Attrs(IOSTANDARD="LVDS"),
163-
attrs=Attrs(IOSTANDARD="LVCMOS15"),
139+
attrs=Attrs(IOSTANDARD="LVCMOS15")
164140
),
165141
]
166142
connectors = top_connectors + bottom_connectors
@@ -169,26 +145,20 @@ class AlchitryPtV2Platform(XilinxPlatform):
169145
# without bitstream compression
170146
def toolchain_prepare(self, fragment, name, **kwargs):
171147
overrides = {
172-
"script_before_bitstream": "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]\n"
173-
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
148+
"script_before_bitstream":
149+
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]\n"
150+
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
174151
}
175152
return super().toolchain_prepare(fragment, name, **overrides, **kwargs)
176153

177154
# TODO: Support vivado and openocd for programming
178155
def toolchain_program(self, products, name, *, flash=True):
179156
loader = find_loader()
180157
with products.extract(f"{name}.bin") as bitstream_filename:
181-
subprocess.check_call(
182-
[
183-
loader,
184-
"load",
185-
"--board",
186-
"PtV2",
187-
"--bin",
188-
bitstream_filename,
189-
"--flash" if flash else "--ram",
190-
]
191-
)
158+
subprocess.check_call([
159+
loader, "load", "--board", "PtV2", "--bin",
160+
bitstream_filename, "--flash" if flash else "--ram"
161+
])
192162

193163

194164
class AlchitryPtV2AlphaPlatform(AlchitryPtV2Platform):
@@ -197,5 +167,4 @@ class AlchitryPtV2AlphaPlatform(AlchitryPtV2Platform):
197167

198168
if __name__ == "__main__":
199169
from amaranth_boards.test.blinky import Blinky
200-
201170
AlchitryPtV2Platform().build(Blinky(), do_program=True)

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