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Merge pull request #471 from vobst/cast_display_target_size
For a cast expression, the input size does not determine the output size. Thus, include the result size in the string representation of the expression to facilitate easier stateless parsing and debugging.
2 parents 65efd5f + f67d109 commit e8db00b

4 files changed

Lines changed: 9 additions & 9 deletions

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src/cwe_checker_lib/src/intermediate_representation/expression.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -243,7 +243,7 @@ impl fmt::Display for Expression {
243243
_ => write!(f, "({lhs} {op} {rhs})"),
244244
},
245245
Expression::UnOp { op, arg } => write!(f, "{op}({arg})"),
246-
Expression::Cast { op, size: _, arg } => write!(f, "{op}({arg})"),
246+
Expression::Cast { op, size, arg } => write!(f, "{op}({arg}):{size}"),
247247
Expression::Unknown {
248248
description,
249249
size: _,

src/cwe_checker_lib/src/intermediate_representation/expression/tests.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ fn display() {
222222
.subpiece(ByteSize(0), ByteSize(20));
223223

224224
assert_eq!(
225-
"(FloatCeil(IntSExt(-((0x2:4 + RAX:8 * RBP:8)))))[0-19]",
225+
"(FloatCeil(IntSExt(-((0x2:4 + RAX:8 * RBP:8))):8))[0-19]",
226226
format!("{}", expr)
227227
);
228228
}

src/cwe_checker_lib/src/pcode/subregister_substitution/tests.rs

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -287,7 +287,7 @@ fn piecing_or_zero_extending() {
287287
replace_subregister_in_block(&mut block, &register_map);
288288
assert!(check_defs_of_block(
289289
&block,
290-
vec!["zext_eax_to_rax: RAX:8 = IntZExt(0x0:4)"]
290+
vec!["zext_eax_to_rax: RAX:8 = IntZExt(0x0:4):8"]
291291
));
292292

293293
// Test whether zero extension to base register is still recognized
@@ -303,7 +303,7 @@ fn piecing_or_zero_extending() {
303303
replace_subregister_in_block(&mut block, &register_map);
304304
assert!(check_defs_of_block(
305305
&block,
306-
vec!["zext_ah_to_rax: RAX:8 = IntZExt(0x0:1)"]
306+
vec!["zext_ah_to_rax: RAX:8 = IntZExt(0x0:1):8"]
307307
));
308308

309309
// Test when the next register is a zero extension to a different register.
@@ -320,7 +320,7 @@ fn piecing_or_zero_extending() {
320320
&block,
321321
vec![
322322
"eax_assign: RAX:8 = ((RAX:8)[4-7] Piece 0x0:4)",
323-
"zext_eax_to_rcx: RCX:8 = IntZExt((RAX:8)[0-3])"
323+
"zext_eax_to_rcx: RCX:8 = IntZExt((RAX:8)[0-3]):8"
324324
]
325325
));
326326

@@ -338,7 +338,7 @@ fn piecing_or_zero_extending() {
338338
&block,
339339
vec![
340340
"ah_assign: RAX:8 = (((RAX:8)[2-7] Piece 0x0:1) Piece (RAX:8)[0-0])",
341-
"zext_ah_to_eax: RAX:8 = ((RAX:8)[4-7] Piece IntZExt((RAX:8)[1-1]))",
341+
"zext_ah_to_eax: RAX:8 = ((RAX:8)[4-7] Piece IntZExt((RAX:8)[1-1]):4)",
342342
]
343343
));
344344

@@ -356,7 +356,7 @@ fn piecing_or_zero_extending() {
356356
&block,
357357
vec![
358358
"load_to_eax: loaded_value:4(temp) := Load from 0x0:8",
359-
"zext_eax_to_rax: RAX:8 = IntZExt(loaded_value:4(temp))",
359+
"zext_eax_to_rax: RAX:8 = IntZExt(loaded_value:4(temp)):8",
360360
]
361361
));
362362

@@ -375,7 +375,7 @@ fn piecing_or_zero_extending() {
375375
vec![
376376
"load_to_eax: loaded_value:4(temp) := Load from 0x0:8",
377377
"load_to_eax_cast_to_base: RAX:8 = ((RAX:8)[4-7] Piece loaded_value:4(temp))",
378-
"zext_eax_to_rcx: RCX:8 = IntZExt((RAX:8)[0-3])"
378+
"zext_eax_to_rcx: RCX:8 = IntZExt((RAX:8)[0-3]):8"
379379
]
380380
));
381381
}

src/cwe_checker_lib/src/pcode/term/tests.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -805,7 +805,7 @@ fn from_project_to_ir_project() {
805805
);
806806
assert_eq!(
807807
format!("{}", ir_block.defs[3].term),
808-
"RAX:8 = IntZExt((RDI:8)[0-3])".to_string()
808+
"RAX:8 = IntZExt((RDI:8)[0-3]):8".to_string()
809809
);
810810
assert_eq!(
811811
format!("{}", ir_block.defs[4].term),

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