core: add zero and sign extension pseudoinstructions

Author: ldlaur

src/exec/core.c

@@ -786,6 +786,34 @@ const char *handle_alu_reg(Parser *p, const char *opcode, size_t opcode_len) {
     return NULL;
 }
 
+const char *handle_ext(Parser *p, const char *opcode, size_t opcode_len) {
+    int d, s1, s2;
+
+    skip_trailing(p);
+    if ((d = parse_reg(p)) == -1) return "Invalid rd";
+    skip_trailing(p);
+    if (!consume_if(p, ',')) return "Expected ,";
+
+    skip_trailing(p);
+    if ((s1 = parse_reg(p)) == -1) return "Invalid rs1";
+    skip_trailing(p);
+
+    if (str_eq_case(opcode, opcode_len, "zext.b")) {
+        asm_emit(ANDI(d, s1, 255), p->startline);
+    } else if (str_eq_case(opcode, opcode_len, "zext.h")) {
+        asm_emit(SLLI(d, s1, 16), p->startline);
+        asm_emit(SRLI(d, d, 16), p->startline);
+    } else if (str_eq_case(opcode, opcode_len, "sext.b")) {
+        asm_emit(SLLI(d, s1, 24), p->startline);
+        asm_emit(SRAI(d, d, 24), p->startline);
+    } else if (str_eq_case(opcode, opcode_len, "sext.h")) {
+        asm_emit(SLLI(d, s1, 16), p->startline);
+        asm_emit(SRAI(d, d, 16), p->startline);
+    }
+
+    return NULL;
+}
+
 const char *handle_alu_imm(Parser *p, const char *opcode, size_t opcode_len) {
     Parser orig = *p;
     int d, s1;
@@ -1092,7 +1120,7 @@ const char *handle_upper(Parser *p, const char *opcode, size_t opcode_len) {
     } else if (!parse_numeric(p, &simm)) return "Invalid immediate";
     // the immediate can either be signed or unsigned 20 bit
     if (simm < -524288 || simm > 1048575) return "Out of bounds immediate";
-    
+
     if (str_eq_case(opcode, opcode_len, "lui")) inst = LUI(d, simm);
     else if (str_eq_case(opcode, opcode_len, "auipc")) inst = AUIPC(d, simm);
 
@@ -1247,6 +1275,7 @@ OpcodeHandling opcode_types[] = {
     },
     {handle_alu_imm,
      {"addi", "slti", "sltiu", "andi", "ori", "xori", "slli", "srli", "srai"}},
+    {handle_ext, {"sext.b", "sext.h", "zext.b", "zext.h"}},
     {handle_ldst, {"lb", "lh", "lw", "lbu", "lhu", "sb", "sh", "sw"}},
     {handle_branch,
      {"beq", "bne", "blt", "bge", "bltu", "bgeu", "bgt", "ble", "bgtu",

src/webui/IntegratedHelp.tsx

@@ -182,6 +182,14 @@ seqz rd, rs1
 (sltiu rd, rs1, 1)
 rd = (rs1 == 0) ? 1 : 0
 
+sext.b rd, rs1
+(slli rd, rs1, 24; srai rd, rd, 24)
+rd = (int32_t)((int8_t)rs1[7:0])
+
+sext.h rd, rs1
+(slli rd, rs1, 16; srai rd, rd, 16)
+rd = (int32_t)((int16_t)rs1[15:0])
+
 sgtz rd, rs1
 (slt rd, zero, rs1)
 rd = (rs1 > 0) ? 1 : 0
@@ -202,7 +210,7 @@ slti rd, rs1, imm
 rd = (rs1 < imm) ? 1 : 0 (signed)
 
 sltiu rd, rs1, imm
-rd = (rs1 < (uint32_t)sext(imm)) ? 1 : 0 (unsigned, ***)
+rd = (rs1 < sext(imm)) ? 1 : 0 (unsigned, ***)
 
 sltu rd, rs1, rs2
 rd = (rs1 < rs2) ? 1 : 0 (unsigned)
@@ -237,7 +245,15 @@ xor rd, rs1, rs2
 rd = rs1 ^ rs2 
 
 xori rd, rs1, imm
-rd = rs1 ^ imm 
+rd = rs1 ^ imm
+
+zext.b rd, rs1
+(andi rd, rs1, 0xFF)
+rd = rs1[7:0]
+
+zext.h rd, rs1
+(slli rd, rs1, 16; srli rd, rd, 16)
+rd = rs1[15:0]
 `;
 
 const asterisks = `

src/webui/riscv.grammar

@@ -96,6 +96,7 @@ RegisterExpression {
     (
       "add" | "slt" | "sltu" | "and" | "or" | "xor" | "sll" | "srl" | "sub" | "sra" | "mul" | "mulh" | "mulhsu" | "mulhu" | "div" |
               "divu" | "rem" | "remu" |
+      "zext.b" | "zext.h" | "sext.b" | "sext.h" |
       "addi" | "slt" | "sltiu" | "andi" | "ori" | "xori" | "slli" | "srli" | "srai" |
       "lb" | "lh" | "lw" | "lbu" | "lhu" | "sb" | "sh" | "sw" |
       "beq" | "bne" | "blt" | "bge" | "bltu" | "bgeu" | "bgt" | "ble" | "bgtu" | "bleu" |