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bjorn-tore-taraldsenbjorn-tore-taraldsen
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boards: Add nRF54LV10A target
Signed-off-by: Bjørn Tore Taraldsen <bjorn.tore.taraldsen@nordicsemi.no> Signed-off-by: Bartosz Gentkowski <bartosz.gentkowski@nordicsemi.no>
1 parent 0a807c0 commit 4693b58

33 files changed

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‎boards/nordic/bm_nrf54lv10dk/CMakeLists.txt‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
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zephyr_library_sources(init.c)

‎boards/nordic/bm_nrf54lv10dk/Kconfig‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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config BOARD_BM_NRF54LV10DK
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select BOARD_LATE_INIT_HOOK

‎boards/nordic/bm_nrf54lv10dk/Kconfig.bm_nrf54lv10dk‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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config BOARD_BM_NRF54LV10DK
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select SOC_NRF54LV10A_ENGA_CPUAPP if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE || \
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BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT || \
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BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE || \
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BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT

‎boards/nordic/bm_nrf54lv10dk/Kconfig.defconfig‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT
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choice NRF_GRTC_TIMER_SOURCE
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default NRF_GRTC_TIMER_SOURCE_LFLPRC if !$(dt_nodelabel_enabled,lfxo)
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endchoice

‎boards/nordic/bm_nrf54lv10dk/Kconfig.sysbuild‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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config PARTITION_MANAGER
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default n
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if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE || \
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BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT
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choice SOFTDEVICE_SELECTION
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default SOFTDEVICE_S115
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endchoice
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endif # BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE || \
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# BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT
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if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE || \
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BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
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choice SOFTDEVICE_SELECTION
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default SOFTDEVICE_S145
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endchoice
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endif # BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE || \
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# BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
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# Kconfigs for all MCUboot board variants
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if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT || \
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BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
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choice BM_BOOTLOADER
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default BM_BOOTLOADER_MCUBOOT
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endchoice
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choice BM_BOOTLOADER_MCUBOOT_SIGNATURE_TYPE
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default BM_BOOTLOADER_MCUBOOT_SIGNATURE_TYPE_ED25519
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endchoice
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config BM_BOOTLOADER_MCUBOOT_SIGNATURE_USING_KMU
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default y
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choice BM_BOOTLOADER_MCUBOOT_IMG_HASH_ALG
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default BM_BOOT_IMG_HASH_ALG_PURE
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endchoice
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choice BM_FIRMWARE_LOADER
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default BM_FIRMWARE_LOADER_BT_MCUMGR
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endchoice
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config BM_BOOTLOADER_MCUBOOT_FIRMWARE_LOADER_ENTRANCE_BOOT_MODE
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default y
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endif # BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT ||
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# BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
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‎boards/nordic/bm_nrf54lv10dk/bm_nrf54lv10dk_nrf54lv10a_cpuapp_common.dtsi‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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/* Override NCS default. */
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#include "bm_nrf54lv10dk_nrf54lv10a_peripherals.dtsi"
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#include "bm_nrf54lv10dk_nrf54lv10a_oscillator.dtsi"
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/delete-node/ &cpuapp_sram;
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/ {
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compatible = "nordic,bm_nrf54lv10dk_nrf54lv10a-cpuapp";
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model = "Nordic Bare Metal nRF54LV10 DK nRF54LV10 Application MCU";
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chosen {
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zephyr,flash-controller = &rram_controller;
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zephyr,boot-mode = &boot_mode0;
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};
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soc {
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cpuapp_sram: memory@20000080 {
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compatible = "mmio-sram";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Adjusted -0x80 to account for the adjusted start addr, added +320
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* to include the extra bytes above last 1kb boandary at top SRAM
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*/
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reg = <0x20000080 (DT_SIZE_K(191) - 0x80 + 320)>;
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ranges = <0x0 0x20000080 (DT_SIZE_K(191) - 0x80 + 320)>;
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nrf_kmu_reserved_push_area: memory@20000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x20000000 0x80>;
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zephyr,memory-region = "nrf_kmu_reserved_push_area";
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};
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};
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};
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/* Override NCS default to use entire RRAM for application CPU. */
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&cpuapp_rram {
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reg = <0x0 DT_SIZE_K(1012)>;
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};
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&gpregret1 {
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status = "okay";
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boot_mode0: boot_mode@0 {
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compatible = "zephyr,retention";
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status = "okay";
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reg = <0x0 0x1>;
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};
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};

‎boards/nordic/bm_nrf54lv10dk/bm_nrf54lv10dk_nrf54lv10a_cpuapp_s115_softdevice.dts‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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/dts-v1/;
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#include <nordic/nrf54lv10a_enga_cpuapp.dtsi>
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#include "bm_nrf54lv10dk_nrf54lv10a_cpuapp_common.dtsi"
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/ {
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chosen {
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zephyr,flash = &cpuapp_rram;
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zephyr,code-partition = &slot0_partition;
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zephyr,sram = &app_ram;
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};
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};
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&cpuapp_rram {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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slot0_partition: partition@0 {
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label = "slot0";
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reg = <0x00000000 DT_SIZE_K(896)>;
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};
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storage_partition: partition@e0000 {
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compatible = "fixed-subpartitions";
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label = "storage";
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reg = <0x000e0000 DT_SIZE_K(8)>;
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ranges = <0x0 0xe0000 DT_SIZE_K(8)>;
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#address-cells = <1>;
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#size-cells = <1>;
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peer_manager_partition: partition@0 {
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label = "peer_manager";
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reg = <0x00000000 DT_SIZE_K(4)>;
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};
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storage0_partition: partition@1000 {
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label = "storage0";
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reg = <0x00001000 DT_SIZE_K(4)>;
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};
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};
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softdevice_partition: partition@e2000 {
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label = "softdevice";
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reg = <0x000e2000 DT_SIZE_K(107)>;
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};
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};
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};
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&cpuapp_sram {
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status = "okay";
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softdevice_static_ram: sram@0 {
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label = "softdevice_static_ram";
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reg = <0x0 0x1380>;
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};
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softdevice_dynamic_ram: sram@1380 {
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label = "softdevice_dynamic_ram";
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reg = <0x1380 DT_SIZE_K(12)>;
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};
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app_ram: sram@4380 {
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label = "app_ram";
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reg = <0x4380 (DT_SIZE_K(174) + 320)>;
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};
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};

‎boards/nordic/bm_nrf54lv10dk/bm_nrf54lv10dk_nrf54lv10a_cpuapp_s115_softdevice.yaml‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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identifier: bm_nrf54lv10dk/nrf54lv10a/cpuapp/s115_softdevice
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name: Bare_Metal-nRF54LV10-DK-nRF54LV10A-Application-S115-SoftDevice
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- xtools
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- zephyr
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sysbuild: true
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ram: 174
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flash: 896

‎boards/nordic/bm_nrf54lv10dk/bm_nrf54lv10dk_nrf54lv10a_cpuapp_s115_softdevice_defconfig‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_BM_UARTE_CONSOLE=y
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# Remove boot banner
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CONFIG_NCS_BOOT_BANNER=n
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CONFIG_BOOT_BANNER=n
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# Enable MPU
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CONFIG_ARM_MPU=y
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# Enable hardware stack protection
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CONFIG_HW_STACK_PROTECTION=y
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# MPU-based null-pointer dereferencing detection cannot
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# be applied as the (0x0 - 0x400) is unmapped for this target.
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CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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# Enable Cache
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_EXTERNAL_CACHE=y
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# Start SYSCOUNTER on driver init
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CONFIG_NRF_GRTC_START_SYSCOUNTER=y
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# Disable partition manager
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CONFIG_PARTITION_MANAGER_ENABLED=n
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# Disable multithreading
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CONFIG_MULTITHREADING=n
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CONFIG_ZERO_LATENCY_IRQS=y
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# Disable generation of the redundant SW ISR table
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CONFIG_GEN_SW_ISR_TABLE=n
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# Allow FLASH writes
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CONFIG_MPU_ALLOW_FLASH_WRITE=y
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# Shrink
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CONFIG_GPIO=n
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# Enable all NRFX drivers
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CONFIG_NRFX_CLOCK=y
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CONFIG_NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED=y
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CONFIG_NRFX_COMP=y
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# CONFIG_NRFX_LPCOMP=y
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CONFIG_NRFX_EGU10=y
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CONFIG_NRFX_EGU20=y
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CONFIG_NRFX_GPIOTE20=y
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CONFIG_NRFX_GPIOTE30=y
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CONFIG_NRFX_GPPI=y
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CONFIG_NRFX_GRTC=y
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CONFIG_NRFX_POWER=y
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CONFIG_NRFX_RRAMC=y
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CONFIG_NRFX_SAADC=y
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CONFIG_NRFX_SPIM=y
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# CONFIG_NRFX_SPIS=y
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CONFIG_NRFX_SYSTICK=y
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CONFIG_NRFX_TEMP=y
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CONFIG_NRFX_TIMER=y
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CONFIG_NRFX_TWIM=y
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CONFIG_NRFX_UARTE=y
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CONFIG_NRFX_WDT=y

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