diff --git a/softperipheral/include/softperipheral_regif.h b/softperipheral/include/softperipheral_regif.h index 488df93c41..94e6efaa07 100644 --- a/softperipheral/include/softperipheral_regif.h +++ b/softperipheral/include/softperipheral_regif.h @@ -9,7 +9,7 @@ /* Shared between Host and Service, varies between platforms. */ #if defined (NRF54L05_XXAA) || defined (NRF54L09_ENGA_XXAA) || defined (NRF54L10_XXAA) || \ - defined (NRF54L15_XXAA) || defined (NRF54LM20A_ENGA_XXAA) || \ + defined (NRF54L15_XXAA) || defined (NRF54LM20A_ENGA_XXAA) || \ defined (NRF54LV10A_XXAA) || defined (NRF54LM20A_XXAA) #define SP_VPR_EVENT_IDX 20 #define NRF_VPR NRF_VPR00 diff --git a/softperipheral/sCAN/include/hal/nrf_can.h b/softperipheral/sCAN/include/hal/nrf_can.h new file mode 100644 index 0000000000..f82b898a78 --- /dev/null +++ b/softperipheral/sCAN/include/hal/nrf_can.h @@ -0,0 +1,532 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_CAN_H__ +#define NRF_CAN_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOFTPERIPHERAL_CAN (1) +#if SOFTPERIPHERAL_CAN +#include +#define NRF_CAN_Type NRF_SP_CAN_Type +#else +#define NRF_CAN_Type NRF_CAN_Type +#endif + +/** + * @defgroup nrf_can_hal CAN HAL + * @{ + * @brief Hardware access layer for managing the CAN peripheral. + */ + +/** @brief CAN tasks. */ +typedef enum +{ + NRF_CAN_TASK_START = offsetof(NRF_CAN_Type, TASKS_START), /**< Trigger this task to start a request (RX/TX). */ + NRF_CAN_TASK_RESET = offsetof(NRF_CAN_Type, + TASKS_RESET), /**< Trigger this task to reset SCAN to UNINITIALIZED state. */ +} nrf_can_task_t; + +/** @brief CAN events. */ +typedef enum +{ + NRF_CAN_EVENT_TXCOMPLETE = offsetof(NRF_CAN_Type, EVENTS_TXCOMPLETE), /**< TX completed. */ + NRF_CAN_EVENT_RXCOMPLETE = offsetof(NRF_CAN_Type, EVENTS_RXCOMPLETE), /**< RX completed after ID match. */ + NRF_CAN_EVENT_ERRORDETECTED = offsetof(NRF_CAN_Type, EVENTS_ERRORDETECTED), /**< Error detected. */ + NRF_CAN_EVENT_STATECHANGED = offsetof(NRF_CAN_Type, EVENTS_STATECHANGED), /**< CAN controller state changed. */ +} nrf_can_event_t; + +/** @brief CAN interrupt masks. */ +typedef enum +{ + NRF_CAN_INT_TXCOMPLETE_MASK = SP_CAN_INTEN_TXCOMPLETE_Msk, /**< Interrupt on TX complete. */ + NRF_CAN_INT_RXCOMPLETE_MASK = SP_CAN_INTEN_RXCOMPLETE_Msk, /**< Interrupt on RX complete. */ + NRF_CAN_INT_ERRORDETECTED_MASK = SP_CAN_INTEN_ERRORDETECTED_Msk, /**< Interrupt on error detected. */ + NRF_CAN_INT_STATECHANGED_MASK = SP_CAN_INTEN_STATECHANGED_Msk, /**< Interrupt on state change. */ +} nrf_can_int_mask_t; + +/** @brief CAN request types. */ +typedef enum +{ + NRF_CAN_REQUEST_RX = SP_CAN_CONFIG_REQUEST_REQUEST_RX, /**< RX request. */ + NRF_CAN_REQUEST_TX = SP_CAN_CONFIG_REQUEST_REQUEST_TX, /**< TX request. */ +} nrf_can_request_t; + +typedef enum +{ + NRF_CAN_PARSING_NONE = SP_CAN_CONFIG_PARSING_REGGROUP_None, + NRF_CAN_PARSING_TIMING = SP_CAN_CONFIG_PARSING_REGGROUP_Timing, + NRF_CAN_PARSING_MODE = SP_CAN_CONFIG_PARSING_REGGROUP_OperationMode, + NRF_CAN_PARSING_RXFILTER = SP_CAN_CONFIG_PARSING_REGGROUP_RxFilters, +} nrf_can_parsing_t; + +/** @brief CAN operation modes. */ +typedef enum +{ + NRF_CAN_MODE_NORMAL = SP_CAN_CONFIG_MODE_MODE_Normal, + NRF_CAN_MODE_LOOPBACK = SP_CAN_CONFIG_MODE_MODE_Loopback, + NRF_CAN_MODE_LISTENONLY = SP_CAN_CONFIG_MODE_MODE_ListenOnly, + NRF_CAN_MODE_ONESHOT = SP_CAN_CONFIG_MODE_MODE_OneShot, +} nrf_can_mode_t; + +typedef enum +{ + NRF_CAN_STATE_ERRORACTIVE = SP_CAN_STATUS_STATUS_STATE_ERRORACTIVE, + NRF_CAN_STATE_ERRORWARNING = SP_CAN_STATUS_STATUS_STATE_ERRORWARNING, + NRF_CAN_STATE_ERRORPASSIVE = SP_CAN_STATUS_STATUS_STATE_ERRORPASSIVE, + NRF_CAN_STATE_BUSOFF = SP_CAN_STATUS_STATUS_STATE_BUSOFF, + NRF_CAN_STATE_STOPPED = SP_CAN_STATUS_STATUS_STATE_STOPPED, +} nrf_can_state_t; + +/** @brief CAN configuration structure. */ +typedef struct +{ + uint32_t timing; /**< Data Bit Timing and Prescaler. */ + nrf_can_request_t request; /**< Request type (RX/TX). */ + nrf_can_mode_t mode; /**< Operation mode. */ +} nrf_can_config_t; + +typedef struct +{ + uint32_t filter; + uint32_t id_mask; +} nrf_can_rxfilter_t; + +/** @brief CAN frame structure. */ +typedef struct +{ + uint32_t identifier; /**< Frame identifier. */ + uint8_t length; /**< Data length. */ + uint8_t data[8]; /**< Data buffer. */ + uint16_t crc; /**< Frame CRC. */ + bool extended_format; /**< Extended format flag. */ + bool remote_request; /**< Remote request flag. */ +} nrf_can_frame_t; + +NRF_STATIC_INLINE void nrf_can_task_trigger(NRF_CAN_Type * p_reg, nrf_can_task_t task); + +NRF_STATIC_INLINE void nrf_can_task_untrigger(NRF_CAN_Type * p_reg, nrf_can_task_t task); + +NRF_STATIC_INLINE void nrf_can_enable(NRF_CAN_Type * p_reg); + +NRF_STATIC_INLINE void nrf_can_disable(NRF_CAN_Type * p_reg); + +NRF_STATIC_INLINE bool nrf_can_enable_check(NRF_CAN_Type const * p_reg); + +NRF_STATIC_INLINE void nrf_can_event_clear(NRF_CAN_Type * p_reg, nrf_can_event_t event); + +NRF_STATIC_INLINE bool nrf_can_event_check(NRF_CAN_Type const * p_reg, nrf_can_event_t event); + +NRF_STATIC_INLINE uint32_t nrf_can_event_address_get(NRF_CAN_Type const * p_reg, + nrf_can_event_t event); + +NRF_STATIC_INLINE void nrf_can_int_enable(NRF_CAN_Type * p_reg, uint32_t mask); + +NRF_STATIC_INLINE uint32_t nrf_can_int_enable_check(NRF_CAN_Type const * p_reg, uint32_t mask); + +NRF_STATIC_INLINE void nrf_can_int_disable(NRF_CAN_Type * p_reg, uint32_t mask); + +NRF_STATIC_INLINE void nrf_can_rxfilter_set(NRF_CAN_Type * p_reg, + nrf_can_rxfilter_t const * p_rxfilter, + uint8_t index); + +NRF_STATIC_INLINE void nrf_can_rxfilter_get(NRF_CAN_Type const * p_reg, + nrf_can_rxfilter_t * p_rxfilter, + uint8_t index); + +NRF_STATIC_INLINE void nrf_can_rxfilter_usefilter_set(NRF_CAN_Type * p_reg, + uint8_t index, + uint8_t value); + +NRF_STATIC_INLINE bool nrf_can_rxfilter_usefilter_get(NRF_CAN_Type const * p_reg, uint8_t index); + +NRF_STATIC_INLINE void nrf_can_rxfilter_filtermatched_set(NRF_CAN_Type * p_reg, + uint8_t index, + uint8_t value); + +NRF_STATIC_INLINE bool nrf_can_rxfilter_filtermatched_get(NRF_CAN_Type const * p_reg, + uint8_t index); + +NRF_STATIC_INLINE void nrf_can_rxfilter_inmailbox_set(NRF_CAN_Type * p_reg, + uint8_t index, + uint8_t value); + +NRF_STATIC_INLINE bool nrf_can_rxfilter_inmailbox_get(NRF_CAN_Type const * p_reg, uint8_t index); + +NRF_STATIC_INLINE void nrf_can_set_parsing_timing(NRF_CAN_Type * p_reg); + +NRF_STATIC_INLINE void nrf_can_set_parsing_mode(NRF_CAN_Type * p_reg); + +NRF_STATIC_INLINE void nrf_can_set_parsing_rxfilter(NRF_CAN_Type * p_reg); + +NRF_STATIC_INLINE void nrf_can_config_set(NRF_CAN_Type * p_reg, nrf_can_config_t const * p_config); + +NRF_STATIC_INLINE void nrf_can_config_get(NRF_CAN_Type const * p_reg, nrf_can_config_t * p_config); + +NRF_STATIC_INLINE void nrf_can_txframe_set(NRF_CAN_Type * p_reg, + uint8_t idx, + nrf_can_frame_t const * p_frame); + +NRF_STATIC_INLINE void nrf_can_txframe_get(NRF_CAN_Type const * p_reg, + uint8_t idx, + nrf_can_frame_t * p_frame); + +NRF_STATIC_INLINE void nrf_can_rxframe_set(NRF_CAN_Type * p_reg, + uint8_t idx, + nrf_can_frame_t const * p_frame); + +NRF_STATIC_INLINE void nrf_can_rxframe_get(NRF_CAN_Type const * p_reg, + uint8_t idx, + nrf_can_frame_t * p_frame); + +NRF_STATIC_INLINE nrf_can_state_t nrf_can_state_get(NRF_CAN_Type const * p_reg); + +NRF_STATIC_INLINE uint32_t nrf_can_error_get(NRF_CAN_Type const * p_reg); + +NRF_STATIC_INLINE bool nrf_can_status_error_check(uint32_t error_mask); + +NRF_STATIC_INLINE void nrf_can_handshake_set(NRF_CAN_Type * p_reg, uint32_t val, uint8_t idx); + +NRF_STATIC_INLINE uint32_t nrf_can_handshake_get(NRF_CAN_Type const * p_reg, uint8_t idx); + +#ifndef NRF_DECLARE_ONLY + +NRF_STATIC_INLINE void nrf_can_task_trigger(NRF_CAN_Type * p_reg, nrf_can_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +NRF_STATIC_INLINE void nrf_can_task_untrigger(NRF_CAN_Type * p_reg, nrf_can_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x0UL; +} + +NRF_STATIC_INLINE void nrf_can_enable(NRF_CAN_Type * p_reg) +{ + p_reg->ENABLE = SP_CAN_ENABLE_ENABLE_Enabled; +} + +NRF_STATIC_INLINE void nrf_can_disable(NRF_CAN_Type * p_reg) +{ + p_reg->ENABLE = SP_CAN_ENABLE_ENABLE_Disabled; +} + +NRF_STATIC_INLINE bool nrf_can_enable_check(NRF_CAN_Type const * p_reg) +{ + return (bool)(p_reg->ENABLE & SP_CAN_ENABLE_ENABLE_Msk); +} + +NRF_STATIC_INLINE void nrf_can_event_clear(NRF_CAN_Type * p_reg, nrf_can_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); +} + +NRF_STATIC_INLINE bool nrf_can_event_check(NRF_CAN_Type const * p_reg, nrf_can_event_t event) +{ + return nrf_event_check(p_reg, event); +} + +NRF_STATIC_INLINE uint32_t nrf_can_event_address_get(NRF_CAN_Type const * p_reg, + nrf_can_event_t event) +{ + return nrf_task_event_address_get(p_reg, event); +} + +NRF_STATIC_INLINE void nrf_can_int_enable(NRF_CAN_Type * p_reg, uint32_t mask) +{ + p_reg->INTEN |= mask; +} + +NRF_STATIC_INLINE uint32_t nrf_can_int_enable_check(NRF_CAN_Type const * p_reg, uint32_t mask) +{ + return p_reg->INTEN & mask; +} + +NRF_STATIC_INLINE void nrf_can_int_disable(NRF_CAN_Type * p_reg, uint32_t mask) +{ + p_reg->INTEN &= ~mask; +} + +NRF_STATIC_INLINE void nrf_can_rxfilter_set(NRF_CAN_Type * p_reg, + nrf_can_rxfilter_t const * p_rxfilter, + uint8_t index) +{ + p_reg->RXFILTER[index].IDFILTER = p_rxfilter->filter & SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Msk; + p_reg->RXFILTER[index].IDMASK = p_rxfilter->id_mask & SP_CAN_RXFILTER_IDMASK_MASK_Msk; +} + +NRF_STATIC_INLINE void nrf_can_rxfilter_get(NRF_CAN_Type const * p_reg, + nrf_can_rxfilter_t * p_rxfilter, + uint8_t index) +{ + p_rxfilter->filter = p_reg->RXFILTER[index].IDFILTER & SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Msk; + p_rxfilter->id_mask = p_reg->RXFILTER[index].IDMASK & SP_CAN_RXFILTER_IDMASK_MASK_Msk; +} + +NRF_STATIC_INLINE void nrf_can_rxfilter_usefilter_set(NRF_CAN_Type * p_reg, + uint8_t index, + uint8_t value) +{ + p_reg->RXFILTER[index].IDFILTER = (p_reg->RXFILTER[index].IDFILTER & + ~SP_CAN_RXFILTER_IDFILTER_USEFILTER_Msk) | + ((value << SP_CAN_RXFILTER_IDFILTER_USEFILTER_Pos) & + SP_CAN_RXFILTER_IDFILTER_USEFILTER_Msk); +} + +NRF_STATIC_INLINE bool nrf_can_rxfilter_usefilter_get(NRF_CAN_Type const * p_reg, uint8_t index) +{ + if ((p_reg->RXFILTER[index].IDFILTER & SP_CAN_RXFILTER_IDFILTER_USEFILTER_Msk) + >> SP_CAN_RXFILTER_IDFILTER_USEFILTER_Pos) + { + return true; + } + return false; +} + +NRF_STATIC_INLINE void nrf_can_rxfilter_filtermatched_set(NRF_CAN_Type * p_reg, + uint8_t index, + uint8_t value) +{ + p_reg->RXFILTER[index].IDFILTER = (p_reg->RXFILTER[index].IDFILTER & + ~SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Msk) | + ((value << SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Pos) & + SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Msk); +} + +NRF_STATIC_INLINE bool nrf_can_rxfilter_filtermatched_get(NRF_CAN_Type const * p_reg, uint8_t index) +{ + if ((p_reg->RXFILTER[index].IDFILTER & SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Msk) + >> SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Pos) + { + return true; + } + return false; +} + +NRF_STATIC_INLINE void nrf_can_rxfilter_inmailbox_set(NRF_CAN_Type * p_reg, + uint8_t index, + uint8_t value) +{ + p_reg->RXFILTER[index].IDFILTER = (p_reg->RXFILTER[index].IDFILTER & + ~SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Msk) | + ((value << SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Pos) & + SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Msk); +} + +NRF_STATIC_INLINE bool nrf_can_rxfilter_inmailbox_get(NRF_CAN_Type const * p_reg, uint8_t index) +{ + if ((p_reg->RXFILTER[index].IDFILTER & SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Msk) + >> SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Pos) + { + return true; + } + return false; +} + +NRF_STATIC_INLINE void nrf_can_set_parsing_timing(NRF_CAN_Type * p_reg) +{ + p_reg->CONFIG.PARSING = NRF_CAN_PARSING_TIMING; +} + +NRF_STATIC_INLINE void nrf_can_set_parsing_mode(NRF_CAN_Type * p_reg) +{ + p_reg->CONFIG.PARSING = NRF_CAN_PARSING_MODE; +} + +NRF_STATIC_INLINE void nrf_can_set_parsing_rxfilter(NRF_CAN_Type * p_reg) +{ + p_reg->CONFIG.PARSING = NRF_CAN_PARSING_RXFILTER; +} + +NRF_STATIC_INLINE void nrf_can_config_set(NRF_CAN_Type * p_reg, nrf_can_config_t const * p_config) +{ + p_reg->CONFIG.TIMING = p_config->timing; + p_reg->CONFIG.REQUEST = ((uint32_t)p_config->request) & + SP_CAN_CONFIG_REQUEST_REQUEST_Msk; + p_reg->CONFIG.MODE = (((uint32_t)p_config->mode) & + SP_CAN_CONFIG_MODE_MODE_Msk); +} + +NRF_STATIC_INLINE void nrf_can_config_get(NRF_CAN_Type const * p_reg, nrf_can_config_t * p_config) +{ + p_config->timing = p_reg->CONFIG.TIMING; + p_config->request = (nrf_can_request_t)(p_reg->CONFIG.REQUEST & + SP_CAN_CONFIG_REQUEST_REQUEST_Msk); + p_config->mode = (nrf_can_mode_t)(p_reg->CONFIG.MODE & + SP_CAN_CONFIG_MODE_MODE_Msk); +} + +NRF_STATIC_INLINE void nrf_can_txframe_set(NRF_CAN_Type * p_reg, + uint8_t idx, + nrf_can_frame_t const * p_frame) +{ + p_reg->TXFRAME[idx].IDENTIFIER = (p_frame->identifier + << SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Pos) & + SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Msk; + + p_reg->TXFRAME[idx].TXDATAL = ((uint32_t)p_frame->data[0] << 0) | ((uint32_t)p_frame->data[1] + << 8) | + ((uint32_t)p_frame->data[2] + << 16) | ((uint32_t)p_frame->data[3] << 24); + + p_reg->TXFRAME[idx].TXDATAH = ((uint32_t)p_frame->data[4] << 0) | ((uint32_t)p_frame->data[5] + << 8) | + ((uint32_t)p_frame->data[6] + << 16) | ((uint32_t)p_frame->data[7] << 24); + + p_reg->TXFRAME[idx].METADATA = (((uint32_t)p_frame->extended_format + << SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Pos) & + SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Msk) | + (((uint32_t)p_frame->remote_request + << SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Pos) & + SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Msk) | + (((uint32_t)p_frame->length + << SP_CAN_TXFRAME_METADATA_DATALENGTH_Pos) & + SP_CAN_TXFRAME_METADATA_DATALENGTH_Msk) | + (((uint32_t)p_frame->crc << SP_CAN_TXFRAME_METADATA_CRC_Pos) & + SP_CAN_TXFRAME_METADATA_CRC_Msk); +} + +NRF_STATIC_INLINE void nrf_can_txframe_get(NRF_CAN_Type const * p_reg, + uint8_t idx, + nrf_can_frame_t * p_frame) +{ + uint32_t identifier = p_reg->TXFRAME[idx].IDENTIFIER; + + p_frame->identifier = (identifier & SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Msk) + >> SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Pos; + + uint32_t datal = p_reg->TXFRAME[idx].TXDATAL; + p_frame->data[0] = (uint8_t)(datal >> 0); + p_frame->data[1] = (uint8_t)(datal >> 8); + p_frame->data[2] = (uint8_t)(datal >> 16); + p_frame->data[3] = (uint8_t)(datal >> 24); + + uint32_t datah = p_reg->TXFRAME[idx].TXDATAH; + p_frame->data[4] = (uint8_t)(datah >> 0); + p_frame->data[5] = (uint8_t)(datah >> 8); + p_frame->data[6] = (uint8_t)(datah >> 16); + p_frame->data[7] = (uint8_t)(datah >> 24); + + uint32_t metadata = p_reg->TXFRAME[idx].METADATA; + p_frame->extended_format = (bool)((metadata & SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Msk) + >> SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Pos); + p_frame->remote_request = (bool)((metadata & SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Msk) + >> SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Pos); + p_frame->length = (uint8_t)((metadata & SP_CAN_TXFRAME_METADATA_DATALENGTH_Msk) + >> SP_CAN_TXFRAME_METADATA_DATALENGTH_Pos); + p_frame->crc = (uint16_t)((metadata & SP_CAN_TXFRAME_METADATA_CRC_Msk) + >> SP_CAN_TXFRAME_METADATA_CRC_Pos); +} + +NRF_STATIC_INLINE void nrf_can_rxframe_set(NRF_CAN_Type * p_reg, + uint8_t idx, + nrf_can_frame_t const * p_frame) +{ + p_reg->RXFRAME[idx].IDENTIFIER = (p_frame->identifier + << SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Pos) & + SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Msk; + + p_reg->RXFRAME[idx].RXDATAL = ((uint32_t)p_frame->data[0] << 0) | ((uint32_t)p_frame->data[1] + << 8) | + ((uint32_t)p_frame->data[2] + << 16) | ((uint32_t)p_frame->data[3] << 24); + + p_reg->RXFRAME[idx].RXDATAH = ((uint32_t)p_frame->data[4] << 0) | ((uint32_t)p_frame->data[5] + << 8) | + ((uint32_t)p_frame->data[6] + << 16) | ((uint32_t)p_frame->data[7] << 24); + + p_reg->RXFRAME[idx].METADATA = (((uint32_t)p_frame->extended_format + << SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Pos) & + SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Msk) | + (((uint32_t)p_frame->remote_request + << SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Pos) & + SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Msk) | + (((uint32_t)p_frame->length + << SP_CAN_RXFRAME_METADATA_DATALENGTH_Pos) & + SP_CAN_RXFRAME_METADATA_DATALENGTH_Msk) | + (((uint32_t)p_frame->crc << SP_CAN_RXFRAME_METADATA_CRC_Pos) & + SP_CAN_RXFRAME_METADATA_CRC_Msk); +} + +NRF_STATIC_INLINE void nrf_can_rxframe_get(NRF_CAN_Type const * p_reg, + uint8_t idx, + nrf_can_frame_t * p_frame) +{ + uint32_t identifier = p_reg->RXFRAME[idx].IDENTIFIER; + + p_frame->identifier = (identifier & SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Msk) + >> SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Pos; + + uint32_t datal = p_reg->RXFRAME[idx].RXDATAL; + p_frame->data[0] = (uint8_t)(datal >> 0); + p_frame->data[1] = (uint8_t)(datal >> 8); + p_frame->data[2] = (uint8_t)(datal >> 16); + p_frame->data[3] = (uint8_t)(datal >> 24); + + uint32_t datah = p_reg->RXFRAME[idx].RXDATAH; + p_frame->data[4] = (uint8_t)(datah >> 0); + p_frame->data[5] = (uint8_t)(datah >> 8); + p_frame->data[6] = (uint8_t)(datah >> 16); + p_frame->data[7] = (uint8_t)(datah >> 24); + + uint32_t metadata = p_reg->RXFRAME[idx].METADATA; + p_frame->extended_format = (bool)((metadata & SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Msk) + >> SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Pos); + p_frame->remote_request = (bool)((metadata & SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Msk) + >> SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Pos); + p_frame->length = (uint8_t)((metadata & SP_CAN_RXFRAME_METADATA_DATALENGTH_Msk) + >> SP_CAN_RXFRAME_METADATA_DATALENGTH_Pos); + p_frame->crc = (uint16_t)((metadata & SP_CAN_RXFRAME_METADATA_CRC_Msk) + >> SP_CAN_RXFRAME_METADATA_CRC_Pos); +} + +NRF_STATIC_INLINE nrf_can_state_t nrf_can_state_get(NRF_CAN_Type const * p_reg) +{ + return (p_reg->STATUS.STATUS & SP_CAN_STATUS_STATUS_STATE_Msk) + >> SP_CAN_STATUS_STATUS_STATE_Pos; +} + +NRF_STATIC_INLINE uint32_t nrf_can_error_get(NRF_CAN_Type const * p_reg) +{ + return (p_reg->STATUS.STATUS & 0x1FF); +} + +NRF_STATIC_INLINE bool nrf_can_status_error_check(uint32_t error_mask) +{ + return (error_mask & + (SP_CAN_STATUS_STATUS_BITERROR_Msk | SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Msk | + SP_CAN_STATUS_STATUS_FORMERROR_Msk | SP_CAN_STATUS_STATUS_ACKERROR_Msk | + SP_CAN_STATUS_STATUS_CRCERROR_Msk | SP_CAN_STATUS_STATUS_PROTOCOLERROR_Msk)) != + 0; +} + +NRF_STATIC_INLINE void nrf_can_handshake_set(NRF_CAN_Type * p_reg, uint32_t val, uint8_t idx) +{ + p_reg->SPSYNC.AUX[idx] = val; +} + +NRF_STATIC_INLINE uint32_t nrf_can_handshake_get(NRF_CAN_Type const * p_reg, uint8_t idx) +{ + return p_reg->SPSYNC.AUX[idx]; +} + +#endif // NRF_DECLARE_ONLY + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_CAN_H__ diff --git a/softperipheral/sCAN/include/nrf54l/scan_firmware.h b/softperipheral/sCAN/include/nrf54l/scan_firmware.h new file mode 100644 index 0000000000..2584a3e4cb --- /dev/null +++ b/softperipheral/sCAN/include/nrf54l/scan_firmware.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SCAN_FIRMWARE_H__ +#define SCAN_FIRMWARE_H__ +#include "scan_firmware_v0.1.0.h" +#define SOFTPERIPHERAL_META_HEADER_VERSION 2 +#endif diff --git a/softperipheral/sCAN/include/nrf54l/scan_firmware_v0.1.0.h b/softperipheral/sCAN/include/nrf54l/scan_firmware_v0.1.0.h new file mode 100644 index 0000000000..15d4c8804c --- /dev/null +++ b/softperipheral/sCAN/include/nrf54l/scan_firmware_v0.1.0.h @@ -0,0 +1,1208 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SP_SCAN_FIRMWARE_H__ +#define SP_SCAN_FIRMWARE_H__ + +#include + +const uint8_t scan_firmware_bin[] = { + 0x05, 0xa0, 0x12, 0x00, 0xa2, 0x5c, 0x08, 0x22, 0x00, 0x00, 0x01, 0x00, + 0xc0, 0x03, 0x80, 0x00, 0x7a, 0xda, 0xe5, 0x12, 0x00, 0x3c, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x06, 0x7a, 0xda, 0xe5, 0x12, 0x97, 0x02, 0x00, 0x00, + 0x81, 0x12, 0x03, 0xa3, 0xc2, 0x1e, 0x63, 0x02, 0x03, 0x06, 0x23, 0xa6, + 0x02, 0x1e, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xe3, 0x9c, 0x16, 0x93, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x03, 0x9a, 0x96, 0x93, 0x81, 0x45, + 0x7d, 0x56, 0x63, 0x0d, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x07, + 0xb5, 0x00, 0x63, 0x05, 0xc5, 0x00, 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, + 0x11, 0x03, 0xe5, 0xb7, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x43, 0x9b, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x83, 0x9a, 0xf1, 0x13, 0x81, 0x45, + 0x63, 0x0b, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x05, 0xb5, 0x00, + 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, 0x11, 0x03, 0xf5, 0xb7, 0x97, 0x11, + 0x00, 0x00, 0x83, 0xa1, 0x21, 0x94, 0x17, 0x11, 0x00, 0x00, 0x03, 0x21, + 0xa1, 0x99, 0x33, 0x04, 0x01, 0x00, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x62, 0x98, 0x73, 0x90, 0x72, 0x30, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x91, 0x73, 0x90, 0x52, 0x30, 0x73, 0x10, 0x20, 0x34, 0x97, 0x12, + 0x00, 0x00, 0x83, 0xa2, 0x22, 0x98, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, + 0x63, 0x94, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x23, 0x92, 0x89, 0x28, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x42, 0x91, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0xc3, 0x94, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xc3, 0x91, + 0x25, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0xe2, 0x92, 0x17, 0x13, + 0x00, 0x00, 0x03, 0x23, 0xa3, 0x92, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, + 0x63, 0x90, 0x39, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x42, 0x90, + 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x83, 0x92, 0x97, 0x13, 0x00, 0x00, + 0x83, 0xa3, 0xc3, 0x8c, 0x11, 0x20, 0x21, 0xa8, 0x63, 0x8a, 0x62, 0x00, + 0x03, 0xa5, 0x03, 0x00, 0x23, 0xa0, 0xa2, 0x00, 0x91, 0x02, 0x91, 0x03, + 0xe3, 0x9a, 0x62, 0xfe, 0x82, 0x80, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x8d, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xe3, 0x8a, 0x25, 0x20, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x02, 0x89, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0x43, 0x8a, 0x19, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x62, 0x89, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xe3, 0x8c, 0x11, 0x20, + 0x09, 0xa8, 0x63, 0x87, 0x62, 0x00, 0x23, 0xa0, 0x02, 0x00, 0x91, 0x02, + 0xe3, 0x9d, 0x62, 0xfe, 0x82, 0x80, 0xef, 0x30, 0x20, 0x53, 0xef, 0x00, + 0x70, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0xe0, 0x37, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0xe8, 0x37, 0x00, 0x00, 0x08, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe8, 0x37, 0x00, 0x00, 0x08, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe8, 0x37, 0x00, 0x00, 0x08, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x3c, 0x00, 0x00, 0x37, 0x00, 0x00, 0x00, 0xe4, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xe4, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff +}; +const uint32_t scan_firmware_bin_len = 14312; +#endif // SP_SCAN_FIRMWARE_H__ diff --git a/softperipheral/sCAN/include/nrf_config_scan.h b/softperipheral/sCAN/include/nrf_config_scan.h new file mode 100644 index 0000000000..9510300ddc --- /dev/null +++ b/softperipheral/sCAN/include/nrf_config_scan.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_SCAN_CONFIG_H__ +#define NRF_SCAN_CONFIG_H__ + +/** + * @brief NRF_SCAN_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRF_SCAN_ENABLED +#define NRF_SCAN_ENABLED 0 +#endif + +/** + * ,* @brief NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE ,* + * ,* Integer value. Maximum size of the RXFILTER buffer + * ,*/ +#ifndef NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE +#define NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE 4 +#endif // NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE + +/** + * @brief NRF_SCAN_MAX_DATA_LENGTH + * + * Integer value. Maximum number of bytes to send in a TX attempt + */ +#ifndef NRF_SCAN_MAX_DATA_LENGTH +#define NRF_SCAN_MAX_DATA_LENGTH 8 +#endif // NRF_SCAN_MAX_DATA_LENGTH + +#endif // NRF_SCAN_CONFIG_H__ diff --git a/softperipheral/sCAN/include/nrf_scan.h b/softperipheral/sCAN/include/nrf_scan.h new file mode 100644 index 0000000000..77878c50c3 --- /dev/null +++ b/softperipheral/sCAN/include/nrf_scan.h @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_SCAN_H__ +#define NRF_SCAN_H__ + +#include +#include +// #include "nrf_config_scan.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_scan Soft CAN + * @{ + * + * @brief Soft CAN driver + * + * This API describes the driver operation of a Software CAN emulated in a VPR CPU. Based on CAN2.0A/B standard. + * + * The functions in this driver are not reentrant if they operate on the same sCAN peripheral. It is + * the responsibility of the API user to ensure the functions are not preempted by each other. + * An exception is the callback function context. Multiple functions from this API can be called + * from the callback. + * + * @note The nrf_scan_irq_handler() function must be called from an external IRQ handler that has + * been properly registered with the interrupt controller system. + * + * @note The GPIO pins required for sCAN operation must be properly configured by the user before + * initializing the driver with nrf_scan_init(). + */ + +/** @brief sCAN event definitions */ +typedef enum +{ + NRF_SCAN_EVT_TX_COMPLETE, ///< TX has finished, if mode is ONESHOT this happens even if there are errors or arbitration was lost + NRF_SCAN_EVT_RX_COMPLETE, ///< RX has finished after an ID match + NRF_SCAN_EVT_ERROR, ///< sCAN has detected an error + NRF_SCAN_EVT_STATE_CHANGED, ///< sCAN state has changed +} nrf_scan_event_type_t; + +/** @brief sCAN operation mode definitions */ +typedef enum +{ + NRF_SCAN_MODE_NORMAL = 0, ///< Normal mode of operation, RX/TX, uses ID filters, TX will be attemted until success + NRF_SCAN_MODE_LOOPBACK, ///< To test API, moves TX data to RX data via SW + NRF_SCAN_MODE_LISTENONLY, ///< Listen only mode of operation, can't send dominant + ///< bits + NRF_SCAN_MODE_ONESHOT, ///< Same as normal mode of operation but TX attempts happen only + ///< once +} nrf_scan_mode_type_t; + +/** @brief sCAN error code definitions */ +typedef enum +{ + NRF_SCAN_SUCCESS = 0, + NRF_SCAN_ERROR_PROTOCOL, ///< Generic error response. + NRF_SCAN_ERROR_BIT_STUFFING_ERROR, ///< RX. Node receives 6 consecutive dominant/recessive bits between SOF and CRC. + NRF_SCAN_ERROR_BIT0_ERROR, ///< TX. Node can't send dominant bit. + NRF_SCAN_ERROR_BIT1_ERROR, ///< TX. Node can't send recessive bit. + NRF_SCAN_ERROR_FORM_ERROR, ///< RX. Node receives an invalid value in a bit that belongs to SOF/EOF fields or ACK/CRC delimiters. + NRF_SCAN_ERROR_ACK_ERROR, ///< TX. Node transmits message but ACK slot is not made dominant by receivers + NRF_SCAN_ERROR_CRC_ERROR, ///< RX. Node calculates message CRC that differs from the one sent + NRF_SCAN_ERROR_BUSY, ///< API level error. sCAN is busy + NRF_SCAN_ERROR_UNSUPPORTED, ///< API level error. Config parameter combination is not supported + NRF_SCAN_ERROR_INVALID_PARAM, ///< API level error. Invalid config parameter + NRF_SCAN_ERROR_INVALID_STATE, ///< API level error. nrfx driver in invalid state +} nrf_scan_error_t; + +/** @brief sCAN state definitions */ +typedef enum +{ + NRF_SCAN_STATE_ERROR_ACTIVE = 0, ///< TEC/REC < 96 + NRF_SCAN_STATE_ERROR_WARNING, ///< TEC/REC < 128 + NRF_SCAN_STATE_ERROR_PASSIVE, ///< TEC/REC < 256 + NRF_SCAN_STATE_BUS_OFF, ///< TEC/REC >= 256 + NRF_SCAN_STATE_STOPPED, ///< No participation in CAN communication +} nrf_scan_state_t; + +/** @brief sCAN event handler function pointer */ +typedef void (* nrf_scan_event_handler_t)(nrf_scan_event_type_t const * p_event, + void * p_context); + +/** + * ,* @brief sCAN context structure. + * ,*/ +typedef struct +{ + uint16_t sp_identifier; ///< Soft peripheral identifier + uint16_t + last_updated_mailbox; ///< index corresponding to the last updated mailbox, populated when NRF_SCAN_EVT_RX_COMPLETE happens +} nrf_scan_context_t; + +/** + * ,* @brief sCAN timing configuration structure. + * ,*/ +typedef struct +{ + uint16_t sjw; ///< (Re)synchronization jump width in quanta units + uint16_t prop_seg; ///< Propagation segment length in quanta units + uint16_t phase_seg1; ///< Phase segment 1 length in quanta units + uint16_t phase_seg2; ///< Phase segment 2 length in quanta units + uint16_t prescaler; ///< Prescaler, number of clock cycles per quanta unit +} nrf_scan_timing_t; + +/** + * ,* @brief sCAN TX/RX frame structure. + * ,*/ +typedef struct +{ + uint32_t identifier; ///< ID, 11 or 29 bits depending on ide + uint8_t data_length; ///< Data length in bytes [0,8] + uint8_t ide; ///< Identifier Extension bit + uint8_t rtr; ///< Remote Transmission Request bit + uint8_t data[8]; +} nrf_scan_frame_t; + +/** + * ,* @brief sCAN RX filter structure. + * ,*/ +typedef struct +{ + uint32_t id; ///< ID, can be standard or extended + uint32_t mask; ///< Filter mask +} nrf_scan_rx_filter_t; + +/** + * ,* @brief sCAN RX mailbox structure. + * ,*/ +typedef struct +{ + nrf_scan_frame_t rx_frame; ///< Received frame + nrf_scan_rx_filter_t rx_filter; ///< Filter + bool ready; ///< Indicator for new data to be processed +} nrf_scan_rx_mailbox_t; + +/** + * ,* @brief sCAN RX mailbox. + * + * @note This is populated by the sCAN API, user should only read its data after NRF_SCAN_EVT_RX_COMPLETE. + * + * ,*/ +extern nrf_scan_rx_mailbox_t m_scan_rx_mailbox[]; + +/** + * ,* @brief sCAN driver instance structure. + * ,*/ +typedef struct +{ + void * p_reg; ///< Pointer to a structure with sCAN virtual register interface. + uint8_t + drv_inst_idx; ///< Index of the driver instance. For internal use only. +} nrf_scan_t; + +/** + * ,* @brief sCAN status structure. + * ,*/ +typedef struct +{ + nrf_scan_error_t error; ///< CAN errors. + nrf_scan_state_t state; ///< CAN controller state. +} nrf_scan_status_t; + +/** + * @brief Get sCAN state and errors. + * + * @note Typically called only after an event has been received. + * + * @param[in] p_scan Pointer to the sCAN driver instance to initialize. + */ +nrf_scan_status_t nrf_scan_get_status(nrf_scan_t const * p_scan); + +/** + * @brief Initialize the sCAN driver for a given instance. + * + * @note The GPIO pins required for sCAN operation must be properly configured by the API user + * before calling this function. + * + * @param[in] p_scan Pointer to the sCAN driver instance to initialize. + * @param[in] handler Event handler callback function. + * @param[in] p_context User context passed to the event handler. + * + * @retval NRF_SCAN_SUCCESS Initialization successful. + * @retval NRF_SCAN_UNSUPPORTED feature unsupported. + * @retval NRF_SCAN_ERROR_INVALID_PARAM Invalid or NULL parameter provided. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_BUSY sCAN driver is busy + */ +nrf_scan_error_t nrf_scan_init(nrf_scan_t const * p_scan, + nrf_scan_event_handler_t handler, + void * p_context); + +/** + * @brief Uninitialize the sCAN driver instance. + * + * This function deconfigures the peripheral. + * + * @note The function deactivates the peripheral instance if it is active. + * The deactivation process releases the clock requests and the power + * states restrictions related to VPR. + * + * @param[in] p_scan Identifier of the sCAN instance to uninitialize. + */ +void nrf_scan_uninit(nrf_scan_t const * p_scan); + +/** + * @brief Explicitly power up and configure the controller. + * + * Optional: Recommended around sequences of operations to avoid repeated power toggling latency. + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * + * @retval NRF_SCAN_SUCCESS Controller powered up successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + */ +nrf_scan_error_t nrf_scan_enable(nrf_scan_t const * p_scan); + +/** + * @brief Explicitly power down the controller. + * + * This function will abort any ongoing operations by calling @ref nrf_scan_abort + * Optional: Call after a series of operations to save power. + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * + * @retval NRF_SCAN_SUCCESS Controller powered down successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + */ +nrf_scan_error_t nrf_scan_disable(nrf_scan_t const * p_scan); + +/** + * @brief Configure sCAN timing. + * + * This function configures timing parameters for sCAN + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * @param[in] p_timing Pointer to the sCAN driver timing configuration structure. + * + * @note This function must be called after sCAN is in STOPPED state: + * - after @ref nrf_scan_enable + * - after @ref nrf_scan_abort + * + * @note From a cold start, if this function is called after @ref nrf_can_enable, sCAN will immediately start operation with no RX filter + * + * @retval NRF_SCAN_SUCCESS Controller timing configured successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_INVALID_PARAM sCAN timing configuration contains an invalid parameter. + */ +nrf_scan_error_t nrf_scan_timing(nrf_scan_t const * p_scan, + nrf_scan_timing_t const * p_timing); + +/** + * @brief Configure sCAN mode. + * + * This function configures mode of operation for sCAN + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * @param[in] p_mode Pointer to the sCAN driver mode configuration. + * + * @retval NRF_SCAN_SUCCESS Controller mode configured successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_INVALID_PARAM sCAN mode configuration contains an invalid parameter. + */ +nrf_scan_error_t nrf_scan_mode(nrf_scan_t const * p_scan, nrf_scan_mode_type_t * p_mode); + +/** + * @brief Configure a sCAN RX filter. + * + * This function configures a filter for RX mailbox[index] + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * @param[in] p_rxfilter Pointer to the RX filter to apply for mailbox[index]. + * @param[in] index Index for @ref m_scan_rx_mailbox. + * + * @retval NRF_SCAN_SUCCESS RX filter for mailbox[index] configured successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_INVALID_PARAM index is an invalid parameter. + */ +nrf_scan_error_t nrf_scan_set_rx_filter(nrf_scan_t const * p_scan, + nrf_scan_rx_filter_t const * p_rxfilter, + uint8_t index); + +/** + * @brief Disable a sCAN RX filter. + * + * This function disables a filter for RX mailbox[index] + * + * @note This function disables the filter but doesn't change ID or Mask values. + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * @param[in] index Index for @ref m_scan_rx_mailbox. + * + * @retval NRF_SCAN_SUCCESS RX filter for mailbox[index] disabled successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_INVALID_PARAM index is an invalid parameter. + */ +nrf_scan_error_t nrf_scan_disable_rx_filter(nrf_scan_t const * p_scan, uint8_t index); + +/** + * @brief Enable a sCAN RX filter. + * + * This function enables a filter for RX mailbox[index] + * + * @note This function enables the filter but doesn't change ID or Mask values. + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * @param[in] index Index for @ref m_scan_rx_mailbox. + * + * @retval NRF_SCAN_SUCCESS RX filter for mailbox[index] enabled successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_INVALID_PARAM index is an invalid parameter. + */ +nrf_scan_error_t nrf_scan_enable_rx_filter(nrf_scan_t const * p_scan, uint8_t index); + +/** + * @brief Unlock sCAN RX mailbox[index]. + * + * @note This function should be called when the data at RX mailbox[index] has been processed + * and sCAN can overwrite it with new data. The data stored in the mailbox will also be cleared + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * @param[in] index Index for @ref m_scan_rx_mailbox. + * + * @retval NRF_SCAN_SUCCESS RX mailbox[index] unlocked successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_INVALID_PARAM index is an invalid parameter. + */ +nrf_scan_error_t nrf_scan_unlock_rx_mailbox(nrf_scan_t const * p_scan, uint8_t index); + +/** + * @brief sCAN send function. + * + * This function configures the mode of operation and attempts to send a frame on the CAN bus. + * + * @param[in] p_scan Pointer to the sCAN driver instance. + * @param[in] p_tx_frame Pointer to the TX frame structure that will be sent on the bus. + * + * @note This function must not be called before @ref nrf_scan_timing has been called at least once. This function can't be called when mode of operation is LISTENONLY. + * + * @retval NRF_SCAN_SUCCESS TX transaction has been dispatched successfully (does not imply correct reception). + * @retval NRF_SCAN_ERROR_BUSY There is another TX transaction in the queue. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + * @retval NRF_SCAN_ERROR_INVALID_PARAM sCAN configuration contains an invalid parameter. + */ +nrf_scan_error_t nrf_scan_send(nrf_scan_t const * p_scan, + nrf_scan_frame_t * p_tx_frame); + +/** + * @brief Abort any ongoing sCAN operation. + * + * This function forcibly terminates any pending sCAN TX/RX + * operations. It should be used as a recovery mechanism when a command has + * timed out or the driver appears to be in a stuck state. + * + * After calling this function, the driver will attempt to reset internal state + * and hardware, making it ready to accept new TX/RX operations. + * This operation will set sCAN state to STOPPED and reset its internal REC and TEC. + * + * This function is called by @ref nrf_scan_disable + * + * @param p_scan Pointer to the sCAN driver instance. + * + * @retval NRF_SCAN_SUCCESS sCAN aborted successfully. + * @retval NRF_SCAN_ERROR_INVALID_STATE nrfx driver state is invalid. + */ +nrf_scan_error_t nrf_scan_abort(nrf_scan_t const * p_scan); + +/** + * @brief IRQ handler to be called from the sCAN interrupt vector. + */ +void nrf_scan_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SCAN_H__ diff --git a/softperipheral/sCAN/include/nrf_sp_can.h b/softperipheral/sCAN/include/nrf_sp_can.h new file mode 100644 index 0000000000..b96948a51a --- /dev/null +++ b/softperipheral/sCAN/include/nrf_sp_can.h @@ -0,0 +1,702 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_SP_CAN_H__ +#define NRF_SP_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nrfx.h" // Resolve nrfXX_types.h for the correct target to get definitions for __IO, __IOM etc. + +/* =========================================================================================================================== + * ================ SP_CAN ================ + * ===========================================================================================================================*/ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct SP_CAN_CONFIG =================================================== */ +/** + * @brief CONFIG [SP_CAN_CONFIG] SCAN configuration + */ +typedef struct +{ + __IOM uint32_t PARSING; /*!< (@ 0x00000000) SCAN parsing options */ + __IOM uint32_t TIMING; /*!< (@ 0x00000004) SCAN Timing parameters */ + __IOM uint32_t REQUEST; /*!< (@ 0x00000008) (unspecified) */ + __IOM uint32_t MODE; /*!< (@ 0x0000000C) Operation mode */ +} NRF_SP_CAN_CONFIG_Type; /*!< Size = 16 (0x010) */ + +/* SP_CAN_CONFIG_PARSING: SCAN parsing options */ + #define SP_CAN_CONFIG_PARSING_ResetValue (0x00000000UL) /*!< Reset value of PARSING register. */ + +/* REGGROUP @Bits 0..2 : Which register group to parse */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_Pos (0UL) /*!< Position of REGGROUP field. */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_Msk (0x7UL << SP_CAN_CONFIG_PARSING_REGGROUP_Pos) /*!< Bit mask of REGGROUP field. */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_Min (0x0UL) /*!< Min enumerator value of REGGROUP field. */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_Max (0x3UL) /*!< Max enumerator value of REGGROUP field. */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_None (0x0UL) /*!< No parsing */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_Timing (0x1UL) /*!< Parse the timing registers */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_OperationMode (0x2UL) /*!< Parse the operation mode */ + #define SP_CAN_CONFIG_PARSING_REGGROUP_RxFilters (0x3UL) /*!< Parse the RX Filters */ + +/* SP_CAN_CONFIG_TIMING: SCAN Timing parameters */ + #define SP_CAN_CONFIG_TIMING_ResetValue (0x00000000UL) /*!< Reset value of TIMING register. */ + +/* RSYNCJUMPWIDTH @Bits 0..7 : Re-synchronization jump width */ + #define SP_CAN_CONFIG_TIMING_RSYNCJUMPWIDTH_Pos (0UL) /*!< Position of RSYNCJUMPWIDTH field. */ + #define SP_CAN_CONFIG_TIMING_RSYNCJUMPWIDTH_Msk \ + (0xFFUL << SP_CAN_CONFIG_TIMING_RSYNCJUMPWIDTH_Pos) \ + /*!< Bit mask of + * RSYNCJUMPWIDTH field.*/ + +/* PHASESEG1 @Bits 8..15 : Number of time quanta in phase 1 */ + #define SP_CAN_CONFIG_TIMING_PHASESEG1_Pos (8UL) /*!< Position of PHASESEG1 field. */ + #define SP_CAN_CONFIG_TIMING_PHASESEG1_Msk (0xFFUL << SP_CAN_CONFIG_TIMING_PHASESEG1_Pos) /*!< Bit mask of PHASESEG1 field. */ + +/* PHASESEG2 @Bits 16..23 : Number of time quanta in phase 2 */ + #define SP_CAN_CONFIG_TIMING_PHASESEG2_Pos (16UL) /*!< Position of PHASESEG2 field. */ + #define SP_CAN_CONFIG_TIMING_PHASESEG2_Msk (0xFFUL << SP_CAN_CONFIG_TIMING_PHASESEG2_Pos) /*!< Bit mask of PHASESEG2 field. */ + +/* PRESCALER @Bits 24..31 : Data Bit Rate Prescaler */ + #define SP_CAN_CONFIG_TIMING_PRESCALER_Pos (24UL) /*!< Position of PRESCALER field. */ + #define SP_CAN_CONFIG_TIMING_PRESCALER_Msk (0xFFUL << SP_CAN_CONFIG_TIMING_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ + +/* SP_CAN_CONFIG_REQUEST: (unspecified) */ + #define SP_CAN_CONFIG_REQUEST_ResetValue (0x00000000UL) /*!< Reset value of REQUEST register. */ + +/* REQUEST @Bit 0 : Request either TX or RX */ + #define SP_CAN_CONFIG_REQUEST_REQUEST_Pos (0UL) /*!< Position of REQUEST field. */ + #define SP_CAN_CONFIG_REQUEST_REQUEST_Msk (0x1UL << SP_CAN_CONFIG_REQUEST_REQUEST_Pos) /*!< Bit mask of REQUEST field. */ + #define SP_CAN_CONFIG_REQUEST_REQUEST_Min (0x0UL) /*!< Min enumerator value of REQUEST field. */ + #define SP_CAN_CONFIG_REQUEST_REQUEST_Max (0x1UL) /*!< Max enumerator value of REQUEST field. */ + #define SP_CAN_CONFIG_REQUEST_REQUEST_RX (0x0UL) /*!< Only listen */ + #define SP_CAN_CONFIG_REQUEST_REQUEST_TX (0x1UL) /*!< Attempt TX */ + +/* SP_CAN_CONFIG_MODE: Operation mode */ + #define SP_CAN_CONFIG_MODE_ResetValue (0x00000000UL) /*!< Reset value of MODE register. */ + +/* MODE @Bits 0..1 : Operation mode */ + #define SP_CAN_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ + #define SP_CAN_CONFIG_MODE_MODE_Msk (0x3UL << SP_CAN_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ + #define SP_CAN_CONFIG_MODE_MODE_Min (0x0UL) /*!< Min enumerator value of MODE field. */ + #define SP_CAN_CONFIG_MODE_MODE_Max (0x3UL) /*!< Max enumerator value of MODE field. */ + #define SP_CAN_CONFIG_MODE_MODE_Normal (0x0UL) /*!< Normal mode */ + #define SP_CAN_CONFIG_MODE_MODE_Loopback (0x1UL) /*!< Loopback mode */ + #define SP_CAN_CONFIG_MODE_MODE_ListenOnly (0x2UL) /*!< Listen only mode */ + #define SP_CAN_CONFIG_MODE_MODE_OneShot (0x3UL) /*!< One shot mode */ + +/* ================================================= Struct SP_CAN_RXFILTER ================================================== */ +/** + * @brief RXFILTER [SP_CAN_RXFILTER] sCAN RX filters + */ +typedef struct +{ + __IOM uint32_t IDFILTER; /*!< (@ 0x00000000) ID filter for RX */ + __IOM uint32_t IDMASK; /*!< (@ 0x00000004) ID mask filter for RX */ +} NRF_SP_CAN_RXFILTER_Type; /*!< Size = 8 (0x008) */ + #define SP_CAN_RXFILTER_MaxCount (4UL) /*!< Size of RXFILTER[4] array. */ + #define SP_CAN_RXFILTER_MaxIndex (3UL) /*!< Max index of RXFILTER[4] array. */ + #define SP_CAN_RXFILTER_MinIndex (0UL) /*!< Min index of RXFILTER[4] array. */ + +/* SP_CAN_RXFILTER_IDFILTER: ID filter for RX */ + #define SP_CAN_RXFILTER_IDFILTER_ResetValue (0x00000000UL) /*!< Reset value of IDFILTER register. */ + +/* IDENTIFIER @Bits 0..28 : ID to match for RX */ + #define SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Pos (0UL) /*!< Position of IDENTIFIER field. */ + #define SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Msk \ + (0x1FFFFFFFUL << SP_CAN_RXFILTER_IDFILTER_IDENTIFIER_Pos) \ + /*!< Bit mask of + * IDENTIFIER field.*/ + +/* USEFILTER @Bit 29 : Enable the filter to match against a received message */ + #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Pos (29UL) /*!< Position of USEFILTER field. */ + #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Msk \ + (0x1UL << SP_CAN_RXFILTER_IDFILTER_USEFILTER_Pos) \ + /*!< Bit mask of USEFILTER + * field.*/ + #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Min (0x0UL) /*!< Min enumerator value of USEFILTER field. */ + #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Max (0x1UL) /*!< Max enumerator value of USEFILTER field. */ + #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_RXFILTER_IDFILTER_USEFILTER_Enabled (0x1UL) /*!< Enable */ + +/* INMAILBOX @Bit 30 : sCAN driver has put the data in a mailbox */ + #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Pos (30UL) /*!< Position of INMAILBOX field. */ + #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Msk \ + (0x1UL << SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Pos) \ + /*!< Bit mask of INMAILBOX + * field.*/ + #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Min (0x0UL) /*!< Min enumerator value of INMAILBOX field. */ + #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Max (0x1UL) /*!< Max enumerator value of INMAILBOX field. */ + #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_RXFILTER_IDFILTER_INMAILBOX_Enabled (0x1UL) /*!< Enable */ + +/* FILTERMATCHED @Bit 31 : Indicates that the filter has been matched */ + #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Pos (31UL) /*!< Position of FILTERMATCHED field. */ + #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Msk \ + (0x1UL << SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Pos) \ + /*!< Bit mask of + * FILTERMATCHED field.*/ + #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Min (0x0UL) /*!< Min enumerator value of FILTERMATCHED field. */ + #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Max (0x1UL) /*!< Max enumerator value of FILTERMATCHED field. */ + #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_NoMatch (0x0UL) /*!< No match */ + #define SP_CAN_RXFILTER_IDFILTER_FILTERMATCHED_Match (0x1UL) /*!< Match */ + +/* SP_CAN_RXFILTER_IDMASK: ID mask filter for RX */ + #define SP_CAN_RXFILTER_IDMASK_ResetValue (0x00000000UL) /*!< Reset value of IDMASK register. */ + +/* MASK @Bits 0..28 : ID mask filter for RX */ + #define SP_CAN_RXFILTER_IDMASK_MASK_Pos (0UL) /*!< Position of MASK field. */ + #define SP_CAN_RXFILTER_IDMASK_MASK_Msk (0x1FFFFFFFUL << SP_CAN_RXFILTER_IDMASK_MASK_Pos) /*!< Bit mask of MASK field. */ + +/* ================================================== Struct SP_CAN_TXFRAME ================================================== */ +/** + * @brief TXFRAME [SP_CAN_TXFRAME] sCAN frame configuration + */ +typedef struct +{ + __IOM uint32_t IDENTIFIER; /*!< (@ 0x00000000) Frame Identifier */ + __IOM uint32_t TXDATAL; /*!< (@ 0x00000004) TX data buffer LSB */ + __IOM uint32_t TXDATAH; /*!< (@ 0x00000008) TX data buffer MSB */ + __IOM uint32_t METADATA; /*!< (@ 0x0000000C) Frame's metadata */ +} NRF_SP_CAN_TXFRAME_Type; /*!< Size = 16 (0x010) */ + #define SP_CAN_TXFRAME_MaxCount (4UL) /*!< Size of TXFRAME[4] array. */ + #define SP_CAN_TXFRAME_MaxIndex (3UL) /*!< Max index of TXFRAME[4] array. */ + #define SP_CAN_TXFRAME_MinIndex (0UL) /*!< Min index of TXFRAME[4] array. */ + +/* SP_CAN_TXFRAME_IDENTIFIER: Frame Identifier */ + #define SP_CAN_TXFRAME_IDENTIFIER_ResetValue (0x00000000UL) /*!< Reset value of IDENTIFIER register. */ + +/* IDENTIFIER @Bits 0..28 : Frame Identifier */ + #define SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Pos (0UL) /*!< Position of IDENTIFIER field. */ + #define SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Msk \ + (0x1FFFFFFFUL << SP_CAN_TXFRAME_IDENTIFIER_IDENTIFIER_Pos) \ + /*!< Bit mask of + * IDENTIFIER field.*/ + +/* SP_CAN_TXFRAME_TXDATAL: TX data buffer LSB */ + #define SP_CAN_TXFRAME_TXDATAL_ResetValue (0x00000000UL) /*!< Reset value of TXDATAL register. */ + +/* TXDATA0 @Bits 0..7 : Data */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA0_Pos (0UL) /*!< Position of TXDATA0 field. */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA0_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA0_Pos) /*!< Bit mask of TXDATA0 field. */ + +/* TXDATA1 @Bits 8..15 : Data */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA1_Pos (8UL) /*!< Position of TXDATA1 field. */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA1_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA1_Pos) /*!< Bit mask of TXDATA1 field. */ + +/* TXDATA2 @Bits 16..23 : Data */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA2_Pos (16UL) /*!< Position of TXDATA2 field. */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA2_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA2_Pos) /*!< Bit mask of TXDATA2 field. */ + +/* TXDATA3 @Bits 24..31 : Data */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA3_Pos (24UL) /*!< Position of TXDATA3 field. */ + #define SP_CAN_TXFRAME_TXDATAL_TXDATA3_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAL_TXDATA3_Pos) /*!< Bit mask of TXDATA3 field. */ + +/* SP_CAN_TXFRAME_TXDATAH: TX data buffer MSB */ + #define SP_CAN_TXFRAME_TXDATAH_ResetValue (0x00000000UL) /*!< Reset value of TXDATAH register. */ + +/* TXDATA4 @Bits 0..7 : Data */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA4_Pos (0UL) /*!< Position of TXDATA4 field. */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA4_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA4_Pos) /*!< Bit mask of TXDATA4 field. */ + +/* TXDATA5 @Bits 8..15 : Data */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA5_Pos (8UL) /*!< Position of TXDATA5 field. */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA5_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA5_Pos) /*!< Bit mask of TXDATA5 field. */ + +/* TXDATA6 @Bits 16..23 : Data */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA6_Pos (16UL) /*!< Position of TXDATA6 field. */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA6_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA6_Pos) /*!< Bit mask of TXDATA6 field. */ + +/* TXDATA7 @Bits 24..31 : Data */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA7_Pos (24UL) /*!< Position of TXDATA7 field. */ + #define SP_CAN_TXFRAME_TXDATAH_TXDATA7_Msk (0xFFUL << SP_CAN_TXFRAME_TXDATAH_TXDATA7_Pos) /*!< Bit mask of TXDATA7 field. */ + +/* SP_CAN_TXFRAME_METADATA: Frame's metadata */ + #define SP_CAN_TXFRAME_METADATA_ResetValue (0x00000000UL) /*!< Reset value of METADATA register. */ + +/* EXTENDEDFORMAT @Bit 0 : Frame's IDE (Identifier Extension bit) */ + #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Pos (0UL) /*!< Position of EXTENDEDFORMAT field. */ + #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Msk \ + (0x1UL << SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Pos) \ + /*!< Bit mask of + * EXTENDEDFORMAT field.*/ + #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Min (0x0UL) /*!< Min enumerator value of EXTENDEDFORMAT field. */ + #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Max (0x1UL) /*!< Max enumerator value of EXTENDEDFORMAT field. */ + #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_TXFRAME_METADATA_EXTENDEDFORMAT_Enabled (0x1UL) /*!< Enable */ + +/* REMOTEREQUEST @Bit 1 : Frame's RTR (Remote Transmission request bit) */ + #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Pos (1UL) /*!< Position of REMOTEREQUEST field. */ + #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Msk \ + (0x1UL << SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Pos) \ + /*!< Bit mask of + * REMOTEREQUEST field.*/ + #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Min (0x0UL) /*!< Min enumerator value of REMOTEREQUEST field. */ + #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Max (0x1UL) /*!< Max enumerator value of REMOTEREQUEST field. */ + #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_TXFRAME_METADATA_REMOTEREQUEST_Enabled (0x1UL) /*!< Enable */ + +/* DATALENGTH @Bits 2..5 : Frame's DLC (Data Length Code) */ + #define SP_CAN_TXFRAME_METADATA_DATALENGTH_Pos (2UL) /*!< Position of DATALENGTH field. */ + #define SP_CAN_TXFRAME_METADATA_DATALENGTH_Msk (0xFUL << SP_CAN_TXFRAME_METADATA_DATALENGTH_Pos) /*!< Bit mask of DATALENGTH + * field.*/ + +/* CRC @Bits 16..30 : Frame's CRC */ + #define SP_CAN_TXFRAME_METADATA_CRC_Pos (16UL) /*!< Position of CRC field. */ + #define SP_CAN_TXFRAME_METADATA_CRC_Msk (0x7FFFUL << SP_CAN_TXFRAME_METADATA_CRC_Pos) /*!< Bit mask of CRC field. */ + +/* ================================================== Struct SP_CAN_RXFRAME ================================================== */ +/** + * @brief RXFRAME [SP_CAN_RXFRAME] sCAN frame configuration + */ +typedef struct +{ + __IOM uint32_t IDENTIFIER; /*!< (@ 0x00000000) Frame Identifier */ + __IOM uint32_t RXDATAL; /*!< (@ 0x00000004) RX data buffer LSB */ + __IOM uint32_t RXDATAH; /*!< (@ 0x00000008) RX data buffer MSB */ + __IOM uint32_t METADATA; /*!< (@ 0x0000000C) Frame's metadata */ +} NRF_SP_CAN_RXFRAME_Type; /*!< Size = 16 (0x010) */ + #define SP_CAN_RXFRAME_MaxCount (4UL) /*!< Size of RXFRAME[4] array. */ + #define SP_CAN_RXFRAME_MaxIndex (3UL) /*!< Max index of RXFRAME[4] array. */ + #define SP_CAN_RXFRAME_MinIndex (0UL) /*!< Min index of RXFRAME[4] array. */ + +/* SP_CAN_RXFRAME_IDENTIFIER: Frame Identifier */ + #define SP_CAN_RXFRAME_IDENTIFIER_ResetValue (0x00000000UL) /*!< Reset value of IDENTIFIER register. */ + +/* IDENTIFIER @Bits 0..28 : Frame Identifier */ + #define SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Pos (0UL) /*!< Position of IDENTIFIER field. */ + #define SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Msk \ + (0x1FFFFFFFUL << SP_CAN_RXFRAME_IDENTIFIER_IDENTIFIER_Pos) \ + /*!< Bit mask of + * IDENTIFIER field.*/ + +/* SP_CAN_RXFRAME_RXDATAL: RX data buffer LSB */ + #define SP_CAN_RXFRAME_RXDATAL_ResetValue (0x00000000UL) /*!< Reset value of RXDATAL register. */ + +/* RXDATA0 @Bits 0..7 : Data */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA0_Pos (0UL) /*!< Position of RXDATA0 field. */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA0_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA0_Pos) /*!< Bit mask of RXDATA0 field. */ + +/* RXDATA1 @Bits 8..15 : Data */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA1_Pos (8UL) /*!< Position of RXDATA1 field. */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA1_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA1_Pos) /*!< Bit mask of RXDATA1 field. */ + +/* RXDATA2 @Bits 16..23 : Data */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA2_Pos (16UL) /*!< Position of RXDATA2 field. */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA2_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA2_Pos) /*!< Bit mask of RXDATA2 field. */ + +/* RXDATA3 @Bits 24..31 : Data */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA3_Pos (24UL) /*!< Position of RXDATA3 field. */ + #define SP_CAN_RXFRAME_RXDATAL_RXDATA3_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAL_RXDATA3_Pos) /*!< Bit mask of RXDATA3 field. */ + +/* SP_CAN_RXFRAME_RXDATAH: RX data buffer MSB */ + #define SP_CAN_RXFRAME_RXDATAH_ResetValue (0x00000000UL) /*!< Reset value of RXDATAH register. */ + +/* RXDATA4 @Bits 0..7 : Data */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA4_Pos (0UL) /*!< Position of RXDATA4 field. */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA4_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA4_Pos) /*!< Bit mask of RXDATA4 field. */ + +/* RXDATA5 @Bits 8..15 : Data */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA5_Pos (8UL) /*!< Position of RXDATA5 field. */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA5_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA5_Pos) /*!< Bit mask of RXDATA5 field. */ + +/* RXDATA6 @Bits 16..23 : Data */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA6_Pos (16UL) /*!< Position of RXDATA6 field. */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA6_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA6_Pos) /*!< Bit mask of RXDATA6 field. */ + +/* RXDATA7 @Bits 24..31 : Data */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA7_Pos (24UL) /*!< Position of RXDATA7 field. */ + #define SP_CAN_RXFRAME_RXDATAH_RXDATA7_Msk (0xFFUL << SP_CAN_RXFRAME_RXDATAH_RXDATA7_Pos) /*!< Bit mask of RXDATA7 field. */ + +/* SP_CAN_RXFRAME_METADATA: Frame's metadata */ + #define SP_CAN_RXFRAME_METADATA_ResetValue (0x00000000UL) /*!< Reset value of METADATA register. */ + +/* EXTENDEDFORMAT @Bit 0 : Frame's IDE (Identifier Extension bit) */ + #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Pos (0UL) /*!< Position of EXTENDEDFORMAT field. */ + #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Msk \ + (0x1UL << SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Pos) \ + /*!< Bit mask of + * EXTENDEDFORMAT field.*/ + #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Min (0x0UL) /*!< Min enumerator value of EXTENDEDFORMAT field. */ + #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Max (0x1UL) /*!< Max enumerator value of EXTENDEDFORMAT field. */ + #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_RXFRAME_METADATA_EXTENDEDFORMAT_Enabled (0x1UL) /*!< Enable */ + +/* REMOTEREQUEST @Bit 1 : Frame's RTR (Remote Transmission request bit) */ + #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Pos (1UL) /*!< Position of REMOTEREQUEST field. */ + #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Msk \ + (0x1UL << SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Pos) \ + /*!< Bit mask of + * REMOTEREQUEST field.*/ + #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Min (0x0UL) /*!< Min enumerator value of REMOTEREQUEST field. */ + #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Max (0x1UL) /*!< Max enumerator value of REMOTEREQUEST field. */ + #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_RXFRAME_METADATA_REMOTEREQUEST_Enabled (0x1UL) /*!< Enable */ + +/* DATALENGTH @Bits 2..5 : Frame's DLC (Data Length Code) */ + #define SP_CAN_RXFRAME_METADATA_DATALENGTH_Pos (2UL) /*!< Position of DATALENGTH field. */ + #define SP_CAN_RXFRAME_METADATA_DATALENGTH_Msk (0xFUL << SP_CAN_RXFRAME_METADATA_DATALENGTH_Pos) /*!< Bit mask of DATALENGTH + * field.*/ + +/* CRC @Bits 16..30 : Frame's CRC */ + #define SP_CAN_RXFRAME_METADATA_CRC_Pos (16UL) /*!< Position of CRC field. */ + #define SP_CAN_RXFRAME_METADATA_CRC_Msk (0x7FFFUL << SP_CAN_RXFRAME_METADATA_CRC_Pos) /*!< Bit mask of CRC field. */ + +/* ================================================== Struct SP_CAN_STATUS =================================================== */ +/** + * @brief STATUS [SP_CAN_STATUS] SCAN status + */ +typedef struct +{ + __IOM uint32_t STATUS; /*!< (@ 0x00000000) SCAN status register */ +} NRF_SP_CAN_STATUS_Type; /*!< Size = 4 (0x004) */ + +/* SP_CAN_STATUS_STATUS: SCAN status register */ + #define SP_CAN_STATUS_STATUS_ResetValue (0x80000000UL) /*!< Reset value of STATUS register. */ + +/* BITERROR @Bit 0 : Transmitter sends dominant/recessive but reads back recessive/dominant. Unable to transmit + * dominant/recessive */ + + #define SP_CAN_STATUS_STATUS_BITERROR_Pos (0UL) /*!< Position of BITERROR field. */ + #define SP_CAN_STATUS_STATUS_BITERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_BITERROR_Pos) /*!< Bit mask of BITERROR field. */ + +/* BITSTUFFINGERROR @Bit 1 : Receiver detects a sequence of 6 dominant or recessive bits */ + #define SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Pos (1UL) /*!< Position of BITSTUFFINGERROR field. */ + #define SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Msk \ + (0x1UL << SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Pos) \ + /*!< Bit mask of + * BITSTUFFINGERROR field.*/ + +/* FORMERROR @Bit 2 : Receiver detects a bit with invalid logical level in SOF/EOF fields or ACK/CRC delimiters */ + #define SP_CAN_STATUS_STATUS_FORMERROR_Pos (2UL) /*!< Position of FORMERROR field. */ + #define SP_CAN_STATUS_STATUS_FORMERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_FORMERROR_Pos) /*!< Bit mask of FORMERROR field. */ + +/* ACKERROR @Bit 3 : Transmitter sends a message but ACK slot is not maide dominant by receiver(s) */ + #define SP_CAN_STATUS_STATUS_ACKERROR_Pos (3UL) /*!< Position of ACKERROR field. */ + #define SP_CAN_STATUS_STATUS_ACKERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_ACKERROR_Pos) /*!< Bit mask of ACKERROR field. */ + +/* CRCERROR @Bit 4 : Receiver calculates a CRC that differs fomr the transmitted CRC field value */ + #define SP_CAN_STATUS_STATUS_CRCERROR_Pos (4UL) /*!< Position of CRCERROR field. */ + #define SP_CAN_STATUS_STATUS_CRCERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ + +/* BIT0ERROR @Bit 5 : Transmitter sends dominant but reads back recessive. Unable to transmit dominant */ + #define SP_CAN_STATUS_STATUS_BIT0ERROR_Pos (5UL) /*!< Position of BIT0ERROR field. */ + #define SP_CAN_STATUS_STATUS_BIT0ERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_BIT0ERROR_Pos) /*!< Bit mask of BIT0ERROR field. */ + +/* BIT1ERROR @Bit 6 : Transmitter sends recessive but reads back dominant. Unable to transmit recessive */ + #define SP_CAN_STATUS_STATUS_BIT1ERROR_Pos (6UL) /*!< Position of BIT1ERROR field. */ + #define SP_CAN_STATUS_STATUS_BIT1ERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_BIT1ERROR_Pos) /*!< Bit mask of BIT1ERROR field. */ + +/* PROTOCOLERROR @Bit 7 : Generic error response */ + #define SP_CAN_STATUS_STATUS_PROTOCOLERROR_Pos (7UL) /*!< Position of PROTOCOLERROR field. */ + #define SP_CAN_STATUS_STATUS_PROTOCOLERROR_Msk (0x1UL << SP_CAN_STATUS_STATUS_PROTOCOLERROR_Pos) /*!< Bit mask of + * PROTOCOLERROR field.*/ + +/* ARBITRATIONLOST @Bit 8 : TX attempt lost arbitration */ + #define SP_CAN_STATUS_STATUS_ARBITRATIONLOST_Pos (8UL) /*!< Position of ARBITRATIONLOST field. */ + #define SP_CAN_STATUS_STATUS_ARBITRATIONLOST_Msk \ + (0x1UL << SP_CAN_STATUS_STATUS_ARBITRATIONLOST_Pos) \ + /*!< Bit mask of + * ARBITRATIONLOST field.*/ + +/* ARBITRATIONLOSTRXOK @Bit 9 : TX attempt lost arbitration, but there was a match for rx filter */ + #define SP_CAN_STATUS_STATUS_ARBITRATIONLOSTRXOK_Pos (9UL) /*!< Position of ARBITRATIONLOSTRXOK field. */ + #define SP_CAN_STATUS_STATUS_ARBITRATIONLOSTRXOK_Msk \ + (0x1UL << SP_CAN_STATUS_STATUS_ARBITRATIONLOSTRXOK_Pos) \ + /*!< Bit mask of + * ARBITRATIONLOSTRXOK field.*/ + +/* STATE @Bits 29..31 : sCAN state */ + #define SP_CAN_STATUS_STATUS_STATE_Pos (29UL) /*!< Position of STATE field. */ + #define SP_CAN_STATUS_STATUS_STATE_Msk (0x7UL << SP_CAN_STATUS_STATUS_STATE_Pos) /*!< Bit mask of STATE field. */ + #define SP_CAN_STATUS_STATUS_STATE_Min (0x0UL) /*!< Min enumerator value of STATE field. */ + #define SP_CAN_STATUS_STATUS_STATE_Max (0x4UL) /*!< Max enumerator value of STATE field. */ + #define SP_CAN_STATUS_STATUS_STATE_ERRORACTIVE (0x0UL) /*!< Error-active state (REC/TEC < 96) */ + #define SP_CAN_STATUS_STATUS_STATE_ERRORWARNING (0x1UL) /*!< Error-warning state (REC/TEC < 128) */ + #define SP_CAN_STATUS_STATUS_STATE_ERRORPASSIVE (0x2UL) /*!< Error-passive state (REC/TEC < 256) */ + #define SP_CAN_STATUS_STATUS_STATE_BUSOFF (0x3UL) /*!< Bus-off state (REC/TEC >= 256) */ + #define SP_CAN_STATUS_STATUS_STATE_STOPPED (0x4UL) /*!< Stopped state, sCAN doesn't participate in communication */ + +/* ================================================== Struct SP_CAN_SPSYNC =================================================== */ +/** + * @brief SPSYNC [SP_CAN_SPSYNC] Registers used to acknowledge API function calls + */ +typedef struct +{ + __IOM uint32_t AUX[6]; /*!< (@ 0x00000000) Auxiliary registers for XSB macro call handshaking */ +} NRF_SP_CAN_SPSYNC_Type; /*!< Size = 24 (0x018) */ + +/* SP_CAN_SPSYNC_AUX: Auxiliary registers for XSB macro call handshaking */ + #define SP_CAN_SPSYNC_AUX_MaxCount (6UL) /*!< Max size of AUX[6] array. */ + #define SP_CAN_SPSYNC_AUX_MaxIndex (5UL) /*!< Max index of AUX[6] array. */ + #define SP_CAN_SPSYNC_AUX_MinIndex (0UL) /*!< Min index of AUX[6] array. */ + #define SP_CAN_SPSYNC_AUX_ResetValue (0x00000000UL) /*!< Reset value of AUX[6] register. */ + +/* AUX @Bits 0..31 : Auxiliary register */ + #define SP_CAN_SPSYNC_AUX_AUX_Pos (0UL) /*!< Position of AUX field. */ + #define SP_CAN_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << SP_CAN_SPSYNC_AUX_AUX_Pos) /*!< Bit mask of AUX field. */ + +/* ====================================================== Struct SP_CAN ====================================================== */ +/** + * @brief Soft peripheral CAN + */ +typedef struct /*!< SP_CAN Structure */ +{ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Trigger this task to start a request (RX/TX) */ + __OM uint32_t TASKS_RESET; /*!< (@ 0x00000004) Trigger this task to reset SCAN to UNINITIALIZED state*/ + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000008) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_RESET; /*!< (@ 0x0000000C) Subscribe configuration for task RESET */ + __IOM uint32_t EVENTS_TXCOMPLETE; /*!< (@ 0x00000010) This event signals that SCAN has completed a TX + * operation*/ + __IOM uint32_t EVENTS_RXCOMPLETE; /*!< (@ 0x00000014) This event signals that SCAN has finished RX after an + * ID match*/ + __IOM uint32_t EVENTS_ERRORDETECTED; /*!< (@ 0x00000018) This event signals that SCAN has detected an error. */ + __IOM uint32_t EVENTS_STATECHANGED; /*!< (@ 0x0000001C) This event signals that SCAN's state has changed. */ + __IOM uint32_t PUBLISH_TXCOMPLETE; /*!< (@ 0x00000020) Publish configuration for event TXCOMPLETE */ + __IOM uint32_t PUBLISH_RXCOMPLETE; /*!< (@ 0x00000024) Publish configuration for event RXCOMPLETE */ + __IOM uint32_t PUBLISH_ERRORDETECTED; /*!< (@ 0x00000028) Publish configuration for event ERRORDETECTED */ + __IOM uint32_t PUBLISH_STATECHANGED; /*!< (@ 0x0000002C) Publish configuration for event STATECHANGED */ + __IOM uint32_t INTEN; /*!< (@ 0x00000030) Enable or disable interrupt */ + __IOM uint32_t ENABLE; /*!< (@ 0x00000034) Enable the SCAN peripheral */ + __IOM NRF_SP_CAN_CONFIG_Type CONFIG; /*!< (@ 0x00000038) SCAN configuration */ + __IOM NRF_SP_CAN_RXFILTER_Type RXFILTER[4]; /*!< (@ 0x00000048) sCAN RX filters */ + __IOM NRF_SP_CAN_TXFRAME_Type TXFRAME[4]; /*!< (@ 0x00000068) sCAN frame configuration */ + __IOM NRF_SP_CAN_RXFRAME_Type RXFRAME[4]; /*!< (@ 0x000000A8) sCAN frame configuration */ + __IOM NRF_SP_CAN_STATUS_Type STATUS; /*!< (@ 0x000000E8) SCAN status */ + __IOM NRF_SP_CAN_SPSYNC_Type SPSYNC; /*!< (@ 0x000000EC) Registers used to acknowledge API function calls */ +} NRF_SP_CAN_Type; /*!< Size = 260 (0x104) */ + +/* SP_CAN_TASKS_START: Trigger this task to start a request (RX/TX) */ + #define SP_CAN_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Trigger this task to start a request (RX/TX) */ + #define SP_CAN_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define SP_CAN_TASKS_START_TASKS_START_Msk (0x1UL << SP_CAN_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + #define SP_CAN_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define SP_CAN_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define SP_CAN_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + +/* SP_CAN_TASKS_RESET: Trigger this task to reset SCAN to UNINITIALIZED state */ + #define SP_CAN_TASKS_RESET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESET register. */ + +/* TASKS_RESET @Bit 0 : Trigger this task to reset SCAN to UNINITIALIZED state */ + #define SP_CAN_TASKS_RESET_TASKS_RESET_Pos (0UL) /*!< Position of TASKS_RESET field. */ + #define SP_CAN_TASKS_RESET_TASKS_RESET_Msk (0x1UL << SP_CAN_TASKS_RESET_TASKS_RESET_Pos) /*!< Bit mask of TASKS_RESET field. */ + #define SP_CAN_TASKS_RESET_TASKS_RESET_Min (0x1UL) /*!< Min enumerator value of TASKS_RESET field. */ + #define SP_CAN_TASKS_RESET_TASKS_RESET_Max (0x1UL) /*!< Max enumerator value of TASKS_RESET field. */ + #define SP_CAN_TASKS_RESET_TASKS_RESET_Trigger (0x1UL) /*!< Trigger task */ + +/* SP_CAN_SUBSCRIBE_START: Subscribe configuration for task START */ + #define SP_CAN_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define SP_CAN_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_CAN_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SP_CAN_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SP_CAN_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_CAN_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_CAN_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_CAN_SUBSCRIBE_START_EN_Msk (0x1UL << SP_CAN_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_CAN_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_CAN_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_CAN_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SP_CAN_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + +/* SP_CAN_SUBSCRIBE_RESET: Subscribe configuration for task RESET */ + #define SP_CAN_SUBSCRIBE_RESET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESET register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESET will subscribe to */ + #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Msk (0xFFUL << SP_CAN_SUBSCRIBE_RESET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_CAN_SUBSCRIBE_RESET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_CAN_SUBSCRIBE_RESET_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_CAN_SUBSCRIBE_RESET_EN_Msk (0x1UL << SP_CAN_SUBSCRIBE_RESET_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_CAN_SUBSCRIBE_RESET_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_CAN_SUBSCRIBE_RESET_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_CAN_SUBSCRIBE_RESET_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SP_CAN_SUBSCRIBE_RESET_EN_Enabled (0x1UL) /*!< Enable subscription */ + +/* SP_CAN_EVENTS_TXCOMPLETE: This event signals that SCAN has completed a TX operation */ + #define SP_CAN_EVENTS_TXCOMPLETE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_TXCOMPLETE register. */ + +/* EVENTS_TXCOMPLETE @Bit 0 : This event signals that SCAN has completed a TX operation */ + #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Pos (0UL) /*!< Position of EVENTS_TXCOMPLETE field. */ + #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Msk \ + (0x1UL << SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Pos) \ + /*!< Bit mask + * of EVENTS_TXCOMPLETE field.*/ + #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Min (0x0UL) /*!< Min enumerator value of EVENTS_TXCOMPLETE field. */ + #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Max (0x1UL) /*!< Max enumerator value of EVENTS_TXCOMPLETE field. */ + #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SP_CAN_EVENTS_TXCOMPLETE_EVENTS_TXCOMPLETE_Generated (0x1UL) /*!< Event generated */ + +/* SP_CAN_EVENTS_RXCOMPLETE: This event signals that SCAN has finished RX after an ID match */ + #define SP_CAN_EVENTS_RXCOMPLETE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_RXCOMPLETE register. */ + +/* EVENTS_RXCOMPLETE @Bit 0 : This event signals that SCAN has finished RX after an ID match */ + #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Pos (0UL) /*!< Position of EVENTS_RXCOMPLETE field. */ + #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Msk \ + (0x1UL << SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Pos) \ + /*!< Bit mask + * of EVENTS_RXCOMPLETE field.*/ + #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Min (0x0UL) /*!< Min enumerator value of EVENTS_RXCOMPLETE field. */ + #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Max (0x1UL) /*!< Max enumerator value of EVENTS_RXCOMPLETE field. */ + #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SP_CAN_EVENTS_RXCOMPLETE_EVENTS_RXCOMPLETE_Generated (0x1UL) /*!< Event generated */ + +/* SP_CAN_EVENTS_ERRORDETECTED: This event signals that SCAN has detected an error. */ + #define SP_CAN_EVENTS_ERRORDETECTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ERRORDETECTED register. */ + +/* EVENTS_ERRORDETECTED @Bit 0 : This event signals that SCAN has detected an error. */ + #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Pos (0UL) /*!< Position of EVENTS_ERRORDETECTED field. */ + #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Msk \ + (0x1UL << SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Pos) + /*!< Bit mask of EVENTS_ERRORDETECTED field.*/ + #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ERRORDETECTED field.*/ + #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ERRORDETECTED field.*/ + #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SP_CAN_EVENTS_ERRORDETECTED_EVENTS_ERRORDETECTED_Generated (0x1UL) /*!< Event generated */ + +/* SP_CAN_EVENTS_STATECHANGED: This event signals that SCAN's state has changed. */ + #define SP_CAN_EVENTS_STATECHANGED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_STATECHANGED register. */ + +/* EVENTS_STATECHANGED @Bit 0 : This event signals that SCAN's state has changed. */ + #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Pos (0UL) /*!< Position of EVENTS_STATECHANGED field. */ + #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Msk \ + (0x1UL << SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Pos) \ + /*!< + * Bit mask of EVENTS_STATECHANGED field.*/ + #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Min (0x0UL) /*!< Min enumerator value of EVENTS_STATECHANGED field. */ + #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Max (0x1UL) /*!< Max enumerator value of EVENTS_STATECHANGED field. */ + #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SP_CAN_EVENTS_STATECHANGED_EVENTS_STATECHANGED_Generated (0x1UL) /*!< Event generated */ + +/* SP_CAN_PUBLISH_TXCOMPLETE: Publish configuration for event TXCOMPLETE */ + #define SP_CAN_PUBLISH_TXCOMPLETE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_TXCOMPLETE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event TXCOMPLETE will publish to */ + #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_CAN_PUBLISH_TXCOMPLETE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Msk (0x1UL << SP_CAN_PUBLISH_TXCOMPLETE_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SP_CAN_PUBLISH_TXCOMPLETE_EN_Enabled (0x1UL) /*!< Enable publishing */ + +/* SP_CAN_PUBLISH_RXCOMPLETE: Publish configuration for event RXCOMPLETE */ + #define SP_CAN_PUBLISH_RXCOMPLETE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_RXCOMPLETE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event RXCOMPLETE will publish to */ + #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_CAN_PUBLISH_RXCOMPLETE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Msk (0x1UL << SP_CAN_PUBLISH_RXCOMPLETE_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SP_CAN_PUBLISH_RXCOMPLETE_EN_Enabled (0x1UL) /*!< Enable publishing */ + +/* SP_CAN_PUBLISH_ERRORDETECTED: Publish configuration for event ERRORDETECTED */ + #define SP_CAN_PUBLISH_ERRORDETECTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ERRORDETECTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ERRORDETECTED will publish to */ + #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Pos) /*!< Bit mask of CHIDX + * field.*/ + #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_CAN_PUBLISH_ERRORDETECTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Msk (0x1UL << SP_CAN_PUBLISH_ERRORDETECTED_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SP_CAN_PUBLISH_ERRORDETECTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + +/* SP_CAN_PUBLISH_STATECHANGED: Publish configuration for event STATECHANGED */ + #define SP_CAN_PUBLISH_STATECHANGED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_STATECHANGED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event STATECHANGED will publish to */ + #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Msk (0xFFUL << SP_CAN_PUBLISH_STATECHANGED_CHIDX_Pos) /*!< Bit mask of CHIDX field.*/ + #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_CAN_PUBLISH_STATECHANGED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_CAN_PUBLISH_STATECHANGED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_CAN_PUBLISH_STATECHANGED_EN_Msk (0x1UL << SP_CAN_PUBLISH_STATECHANGED_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_CAN_PUBLISH_STATECHANGED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_CAN_PUBLISH_STATECHANGED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_CAN_PUBLISH_STATECHANGED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SP_CAN_PUBLISH_STATECHANGED_EN_Enabled (0x1UL) /*!< Enable publishing */ + +/* SP_CAN_INTEN: Enable or disable interrupt */ + #define SP_CAN_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* TXCOMPLETE @Bit 0 : Enable or disable interrupt for event TXATTEMPTCOMPLETE */ + #define SP_CAN_INTEN_TXCOMPLETE_Pos (0UL) /*!< Position of TXCOMPLETE field. */ + #define SP_CAN_INTEN_TXCOMPLETE_Msk (0x1UL << SP_CAN_INTEN_TXCOMPLETE_Pos) /*!< Bit mask of TXCOMPLETE field. */ + #define SP_CAN_INTEN_TXCOMPLETE_Min (0x0UL) /*!< Min enumerator value of TXCOMPLETE field. */ + #define SP_CAN_INTEN_TXCOMPLETE_Max (0x1UL) /*!< Max enumerator value of TXCOMPLETE field. */ + #define SP_CAN_INTEN_TXCOMPLETE_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_INTEN_TXCOMPLETE_Enabled (0x1UL) /*!< Enable */ + +/* RXCOMPLETE @Bit 1 : Enable or disable interrupt for event RXCOMPLETE */ + #define SP_CAN_INTEN_RXCOMPLETE_Pos (1UL) /*!< Position of RXCOMPLETE field. */ + #define SP_CAN_INTEN_RXCOMPLETE_Msk (0x1UL << SP_CAN_INTEN_RXCOMPLETE_Pos) /*!< Bit mask of RXCOMPLETE field. */ + #define SP_CAN_INTEN_RXCOMPLETE_Min (0x0UL) /*!< Min enumerator value of RXCOMPLETE field. */ + #define SP_CAN_INTEN_RXCOMPLETE_Max (0x1UL) /*!< Max enumerator value of RXCOMPLETE field. */ + #define SP_CAN_INTEN_RXCOMPLETE_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_INTEN_RXCOMPLETE_Enabled (0x1UL) /*!< Enable */ + +/* ERRORDETECTED @Bit 2 : Enable or disable interrupt for event ERRORDETECTED */ + #define SP_CAN_INTEN_ERRORDETECTED_Pos (2UL) /*!< Position of ERRORDETECTED field. */ + #define SP_CAN_INTEN_ERRORDETECTED_Msk (0x1UL << SP_CAN_INTEN_ERRORDETECTED_Pos) /*!< Bit mask of ERRORDETECTED field. */ + #define SP_CAN_INTEN_ERRORDETECTED_Min (0x0UL) /*!< Min enumerator value of ERRORDETECTED field. */ + #define SP_CAN_INTEN_ERRORDETECTED_Max (0x1UL) /*!< Max enumerator value of ERRORDETECTED field. */ + #define SP_CAN_INTEN_ERRORDETECTED_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_INTEN_ERRORDETECTED_Enabled (0x1UL) /*!< Enable */ + +/* STATECHANGED @Bit 3 : Enable or disable interrupt for event STATECHANGED */ + #define SP_CAN_INTEN_STATECHANGED_Pos (3UL) /*!< Position of STATECHANGED field. */ + #define SP_CAN_INTEN_STATECHANGED_Msk (0x1UL << SP_CAN_INTEN_STATECHANGED_Pos) /*!< Bit mask of STATECHANGED field. */ + #define SP_CAN_INTEN_STATECHANGED_Min (0x0UL) /*!< Min enumerator value of STATECHANGED field. */ + #define SP_CAN_INTEN_STATECHANGED_Max (0x1UL) /*!< Max enumerator value of STATECHANGED field. */ + #define SP_CAN_INTEN_STATECHANGED_Disabled (0x0UL) /*!< Disable */ + #define SP_CAN_INTEN_STATECHANGED_Enabled (0x1UL) /*!< Enable */ + +/* SP_CAN_ENABLE: Enable the SCAN peripheral */ + #define SP_CAN_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable SCAN */ + #define SP_CAN_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SP_CAN_ENABLE_ENABLE_Msk (0x1UL << SP_CAN_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SP_CAN_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SP_CAN_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SP_CAN_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SCAN */ + #define SP_CAN_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable SCAN */ + +#endif \ + /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +/* ========================================== End of section using anonymous unions ========================================== */ +#endif /* NRF_SP_CAN_H */ diff --git a/softperipheral/sCAN/src/nrf_scan.c b/softperipheral/sCAN/src/nrf_scan.c new file mode 100644 index 0000000000..3c90370fd4 --- /dev/null +++ b/softperipheral/sCAN/src/nrf_scan.c @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include +#include +#include +#include +#include "nrf_config_scan.h" + +#if defined(NRF_SCAN_ENABLED) && (NRF_SCAN_ENABLED == 1) + +#include +#include +#include +#include + +#ifndef EXCLUDE_SP_FW +#define EXCLUDE_SP_FW 0 +#endif +#if EXCLUDE_SP_FW +static void * nvm_fw_addr = (uint8_t *)SP_VPR_FIRMWARE_ADDRESS; +#else +#include +const void * nvm_fw_addr = (const void *)scan_firmware_bin; +#endif + +#define NRFX_LOG_MODULE CAN +#include +#include +#include + +/******************************* NRF_HAL_CAN_H START ************************/ + +#define SOFTPERIPHERAL_CAN (1) +#if SOFTPERIPHERAL_CAN +#define NRF_CAN_Type NRF_SP_CAN_Type +#else +#define NRF_CAN_Type NRF_CAN_Type +#endif + +static uint32_t m_task_count = 1; +nrf_scan_rx_mailbox_t m_scan_rx_mailbox[NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE]; + +typedef struct +{ + void * p_hw_instance; + nrf_scan_event_handler_t handler; + void * p_context; + nrf_scan_event_type_t evt; + nrfx_drv_state_t state; + + volatile bool transfer_in_progress; + volatile bool prepared_pending; + volatile bool timing_configured; + + struct + { + nrf_can_config_t config; + nrf_can_frame_t tx_frame; + } conf; +} can_control_block_t; + +typedef struct +{ + const nrf_scan_timing_t * p_config; + nrf_scan_frame_t * p_tx_frame; + uint8_t drv_inst_idx; +} nrf_scan_request_data_t; + +#define NRF_SCAN_ENABLED_COUNT (1) +static can_control_block_t m_cb[NRF_SCAN_ENABLED_COUNT] = +{{.state = NRFX_DRV_STATE_UNINITIALIZED}}; +static volatile nrf_scan_request_data_t m_current_request; + +NRF_STATIC_INLINE void sp_handshake_set(void * p_reg, uint32_t val, uint8_t idx) +{ + nrf_can_handshake_set((NRF_CAN_Type *)p_reg, val, idx); +} + +NRF_STATIC_INLINE uint32_t sp_handshake_get(void * p_reg, uint8_t idx) +{ + return nrf_can_handshake_get((NRF_CAN_Type const *)p_reg, idx); +} + +nrf_scan_error_t nrf_scan_init(nrf_scan_t const * p_scan, + nrf_scan_event_handler_t handler, + void * p_context) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + return NRF_SCAN_ERROR_BUSY; + } + + p_cb->transfer_in_progress = false; + p_cb->prepared_pending = false; + + const softperipheral_metadata_t * meta = (const softperipheral_metadata_t *)nvm_fw_addr; +#ifndef UNIT_TEST + memset((void *)p_scan->p_reg, 0, sizeof(NRF_SP_CAN_Type)); + + // Set ENABLE to 1, expect it to become 0 when ready. + nrf_can_enable((NRF_CAN_Type *)p_scan->p_reg); +#endif + uint32_t vpr_init_pc = (uint32_t)p_scan->p_reg - meta->fw_shared_ram_addr_offset - + (meta->fw_code_size << 4); + // Copy firmware and start VPR. + if (meta->self_boot == 0) + { +#ifndef UNIT_TEST + memcpy((void *)vpr_init_pc, nvm_fw_addr, meta->fw_code_size << 4); +#endif + nrf_vpr_initpc_set(NRF_VPR, vpr_init_pc); + } + else + { + nrf_vpr_initpc_set(NRF_VPR, vpr_init_pc); + } + + nrf_vpr_cpurun_set(NRF_VPR, true); +#ifndef UNIT_TEST + while (nrf_can_enable_check((NRF_CAN_Type *)p_scan->p_reg) != false) + { + // Wait for peripheral to become ready to receive communication. + } +#endif + + // Store hardware instance and configuration + p_cb->p_hw_instance = p_scan->p_reg; + + // Store handler and context + p_cb->handler = handler; + p_cb->p_context = p_context; + + NRFX_IRQ_PRIORITY_SET(SP_VPR_IRQn, 1); + + nrf_can_int_enable((NRF_CAN_Type *)p_scan->p_reg, + (NRF_CAN_INT_TXCOMPLETE_MASK | NRF_CAN_INT_RXCOMPLETE_MASK | + NRF_CAN_INT_ERRORDETECTED_MASK | NRF_CAN_INT_STATECHANGED_MASK)); + + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + + return NRF_SCAN_SUCCESS; +} + +bool nrf_scan_init_check(const nrf_scan_t * p_scan) +{ + NRFX_ASSERT(p_scan); + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + return (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); +} + +nrf_scan_error_t nrf_scan_enable(nrf_scan_t const * p_scan) +{ + NRFX_ASSERT(p_scan); + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_INITIALIZED) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + nrf_can_enable((NRF_CAN_Type *)p_cb->p_hw_instance); + + __ASB(p_cb->p_hw_instance); + + nrf_can_event_clear((NRF_CAN_Type *)p_cb->p_hw_instance, NRF_CAN_EVENT_TXCOMPLETE); + nrf_can_event_clear((NRF_CAN_Type *)p_cb->p_hw_instance, NRF_CAN_EVENT_RXCOMPLETE); + nrf_can_event_clear((NRF_CAN_Type *)p_cb->p_hw_instance, NRF_CAN_EVENT_ERRORDETECTED); + nrf_can_event_clear((NRF_CAN_Type *)p_cb->p_hw_instance, NRF_CAN_EVENT_STATECHANGED); + + NRFX_IRQ_ENABLE(SP_VPR_IRQn); + + p_cb->state = NRFX_DRV_STATE_POWERED_ON; + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_abort(nrf_scan_t const * p_scan) +{ + NRFX_ASSERT(p_scan); + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (p_cb->state == NRFX_DRV_STATE_UNINITIALIZED) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + p_cb->prepared_pending = false; + p_cb->timing_configured = false; + p_cb->transfer_in_progress = false; + __SSB(p_cb->p_hw_instance); + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_disable(nrf_scan_t const * p_scan) +{ + NRFX_ASSERT(p_scan); + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + nrf_scan_error_t err = nrf_scan_abort(p_scan); + if (err != NRF_SCAN_SUCCESS) + { + return err; + } + + // while (p_cb->transfer_in_progress) {} + + NRFX_IRQ_DISABLE(SP_VPR_IRQn); + + nrf_can_disable((NRF_CAN_Type *)p_cb->p_hw_instance); + + __ASB(p_cb->p_hw_instance); + + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + + return NRF_SCAN_SUCCESS; +} + +void nrf_scan_uninit(nrf_scan_t const * p_scan) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + //Turn off VPR + if (p_cb->state == NRFX_DRV_STATE_POWERED_ON) + { + nrf_scan_disable(p_scan); + } + + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + + // Stop VPR. + nrf_vpr_cpurun_set(NRF_VPR, false); + + // Reset VPR. + nrf_vpr_debugif_dmcontrol_mask_set( + NRF_VPR, (VPR_DEBUGIF_DMCONTROL_NDMRESET_Active << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos | + VPR_DEBUGIF_DMCONTROL_DMACTIVE_Enabled << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos)); + nrf_vpr_debugif_dmcontrol_mask_set( + NRF_VPR, (VPR_DEBUGIF_DMCONTROL_NDMRESET_Inactive << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos | + VPR_DEBUGIF_DMCONTROL_DMACTIVE_Disabled << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos)); + + p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; +} + +#ifndef MAX +#define MAX(x, y) \ + ({ \ + __auto_type _x = (x); \ + __auto_type _y = (y); \ + _x > _y ? _x : _y; \ + }) +#endif + +#ifndef MIN +#define MIN(x, y) \ + ({ \ + __auto_type _x = (x); \ + __auto_type _y = (y); \ + _x < _y ? _x : _y; \ + }) +#endif + +#define TIMING_PACK(prescaler, phase_seg1, phase_seg2, rsync_jw) \ + (((uint32_t)(prescaler) << 24) | ((uint32_t)(phase_seg2) << 16) | ((uint32_t)(phase_seg1) << 8) \ + | ((uint32_t)(rsync_jw))) + +nrf_scan_error_t nrf_scan_timing(nrf_scan_t const * p_scan, + nrf_scan_timing_t const * p_timing) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + if (!p_timing) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + p_cb->conf.config.request = NRF_CAN_REQUEST_RX; + + if (p_timing->prescaler < 8) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + uint16_t ts1 = p_timing->prop_seg + p_timing->phase_seg1; + uint16_t ts2 = p_timing->phase_seg2; + if ((ts1 < 2) || (ts2 < 1) || (ts1 > 16) || (ts2 > p_timing->phase_seg1)) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + if ((p_timing->sjw < 4) || (p_timing->sjw > MIN(ts1, ts2))) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + p_cb->conf.config.timing = TIMING_PACK(p_timing->prescaler, ts1, ts2, p_timing->sjw); + + //Write to regif + nrf_can_config_set((NRF_CAN_Type *)p_cb->p_hw_instance, &(p_cb->conf.config)); + nrf_can_set_parsing_timing((NRF_CAN_Type *)p_cb->p_hw_instance); + + __CSB(p_cb->p_hw_instance); + + p_cb->timing_configured = true; + m_current_request.drv_inst_idx = p_scan->drv_inst_idx; + m_current_request.p_config = p_timing; + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_mode(nrf_scan_t const * p_scan, nrf_scan_mode_type_t * p_mode) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + if (!p_mode) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + p_cb->conf.config.mode = (nrf_can_mode_t)*p_mode; + nrf_can_config_set((NRF_CAN_Type *)p_cb->p_hw_instance, &(p_cb->conf.config)); + nrf_can_set_parsing_mode((NRF_CAN_Type *)p_cb->p_hw_instance); + + __CSB(p_cb->p_hw_instance); + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_set_rx_filter(nrf_scan_t const * p_scan, + // nrf_scan_config_t const * p_config, + nrf_scan_rx_filter_t const * p_rxfilter, + uint8_t index) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (index >= NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + if ((p_cb->state != NRFX_DRV_STATE_POWERED_ON)) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + //Filter overrides a previous one + memset(&m_scan_rx_mailbox[index], 0, sizeof(m_scan_rx_mailbox[index])); + m_scan_rx_mailbox[index].rx_filter = *p_rxfilter; + + nrf_can_rxfilter_t rxfilter; + rxfilter.filter = p_rxfilter->id; + rxfilter.id_mask = p_rxfilter->mask; + + //Write to regif + nrf_can_rxfilter_set((NRF_CAN_Type *)p_cb->p_hw_instance, &rxfilter, index); + nrf_can_rxfilter_usefilter_set((NRF_CAN_Type *)p_cb->p_hw_instance, index, 1); + nrf_can_rxfilter_filtermatched_set((NRF_CAN_Type *)p_cb->p_hw_instance, index, 0); + nrf_can_rxfilter_inmailbox_set((NRF_CAN_Type *)p_cb->p_hw_instance, index, 0); + nrf_can_set_parsing_rxfilter((NRF_CAN_Type *)p_cb->p_hw_instance); + + __CSB(p_cb->p_hw_instance); + + m_current_request.drv_inst_idx = p_scan->drv_inst_idx; + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_disable_rx_filter(nrf_scan_t const * p_scan, uint8_t index) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (index >= NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + if ((p_cb->state != NRFX_DRV_STATE_POWERED_ON)) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + //Clear filter usefilter bit to disable application at regif + nrf_can_rxfilter_usefilter_set((NRF_SP_CAN_Type *)p_cb->p_hw_instance, index, 0); + nrf_can_set_parsing_rxfilter((NRF_CAN_Type *)p_cb->p_hw_instance); + + __CSB(p_cb->p_hw_instance); + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_enable_rx_filter(nrf_scan_t const * p_scan, uint8_t index) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (index >= NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + if ((p_cb->state != NRFX_DRV_STATE_POWERED_ON)) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + //Clear filter usefilter bit to disable application at regif + nrf_can_rxfilter_usefilter_set((NRF_SP_CAN_Type *)p_cb->p_hw_instance, index, 1); + nrf_can_set_parsing_rxfilter((NRF_CAN_Type *)p_cb->p_hw_instance); + + __CSB(p_cb->p_hw_instance); + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_unlock_rx_mailbox(nrf_scan_t const * p_scan, uint8_t index) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (index >= NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + if ((p_cb->state != NRFX_DRV_STATE_POWERED_ON)) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + //clear ready + m_scan_rx_mailbox[index].ready = false; + + //clear API's mailbox + memset(&m_scan_rx_mailbox[index].rx_frame, 0, sizeof(m_scan_rx_mailbox[index].rx_frame)); + //Clear filter inmailbox bit to allow re-populating m_scan_rx_mailbox at index + nrf_can_rxfilter_inmailbox_set((NRF_SP_CAN_Type *)p_cb->p_hw_instance, index, 0); + //Clear filter matched bit to allow overriding at regif + nrf_can_rxfilter_filtermatched_set((NRF_CAN_Type *)p_cb->p_hw_instance, index, 0); + + nrf_can_set_parsing_rxfilter((NRF_CAN_Type *)p_cb->p_hw_instance); + + __CSB(p_cb->p_hw_instance); + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_send(nrf_scan_t const * p_scan, + nrf_scan_frame_t * p_tx_frame) +{ + NRFX_ASSERT(p_scan); + + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + + if (p_cb->prepared_pending) + { + return NRF_SCAN_ERROR_BUSY; + } + + if ((p_cb->state != NRFX_DRV_STATE_POWERED_ON) || !p_cb->timing_configured) + { + return NRF_SCAN_ERROR_INVALID_STATE; + } + + if (!p_tx_frame) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + nrf_scan_status_t status = nrf_scan_get_status(p_scan); + if ((p_cb->conf.config.mode == NRF_CAN_MODE_LISTENONLY) || + (status.state == NRF_SCAN_STATE_BUS_OFF)) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + + p_cb->conf.config.request = NRF_CAN_REQUEST_TX; + p_cb->conf.tx_frame.identifier = p_tx_frame->identifier; + p_cb->conf.tx_frame.crc = 0; //Just zero out, will be calculated on the fly, may not need after all + if (p_tx_frame->data_length > 8) + { + return NRF_SCAN_ERROR_INVALID_PARAM; + } + p_cb->conf.tx_frame.length = p_tx_frame->data_length; + + memcpy(p_cb->conf.tx_frame.data, p_tx_frame->data, sizeof(p_cb->conf.tx_frame.data)); + p_cb->conf.tx_frame.extended_format = p_tx_frame->ide; + p_cb->conf.tx_frame.remote_request = p_tx_frame->rtr; + + //Write to regif + nrf_can_config_set((NRF_CAN_Type *)p_cb->p_hw_instance, &p_cb->conf.config); + nrf_can_txframe_set((NRF_CAN_Type *)p_cb->p_hw_instance, 0, &p_cb->conf.tx_frame); + + // Store transaction data + m_current_request.p_tx_frame = p_tx_frame; + + p_cb->transfer_in_progress = true; + + nrf_vpr_task_trigger(NRF_VPR, offsetof(NRF_VPR_Type, TASKS_TRIGGER[SP_VPR_TASK_DPPI_0_IDX])); + + return NRF_SCAN_SUCCESS; +} + +nrf_scan_error_t nrf_scan_status_to_err(nrf_scan_t const * p_scan) +{ + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + nrf_scan_error_t err = NRF_SCAN_ERROR_PROTOCOL; + uint32_t raw_error = nrf_can_error_get(p_cb->p_hw_instance); + + if (raw_error == 0x0) + { + err = NRF_SCAN_SUCCESS; + return err; + } + + switch (raw_error) + { + case SP_CAN_STATUS_STATUS_BITSTUFFINGERROR_Msk: + { + err = NRF_SCAN_ERROR_BIT_STUFFING_ERROR; + } break; + case SP_CAN_STATUS_STATUS_BITERROR_Msk | SP_CAN_STATUS_STATUS_BIT0ERROR_Msk: + { + err = NRF_SCAN_ERROR_BIT0_ERROR; + } break; + case SP_CAN_STATUS_STATUS_BITERROR_Msk | SP_CAN_STATUS_STATUS_BIT1ERROR_Msk: + { + err = NRF_SCAN_ERROR_BIT1_ERROR; + } break; + case SP_CAN_STATUS_STATUS_FORMERROR_Msk: + { + err = NRF_SCAN_ERROR_FORM_ERROR; + } break; + case SP_CAN_STATUS_STATUS_ACKERROR_Msk: + { + err = NRF_SCAN_ERROR_ACK_ERROR; + } break; + case SP_CAN_STATUS_STATUS_CRCERROR_Msk: + { + err = NRF_SCAN_ERROR_CRC_ERROR; + } break; + default: + { + err = NRF_SCAN_ERROR_PROTOCOL; + } break; + } + + return err; +} + +nrf_scan_state_t nrf_scan_status_to_state(nrf_scan_t const * p_scan) +{ + can_control_block_t * p_cb = &m_cb[p_scan->drv_inst_idx]; + nrf_scan_state_t state = NRF_SCAN_STATE_ERROR_ACTIVE; + uint32_t raw_state = nrf_can_state_get(p_cb->p_hw_instance); + + switch (raw_state) + { + case NRF_CAN_STATE_ERRORACTIVE: + { + state = NRF_SCAN_STATE_ERROR_ACTIVE; + } break; + case NRF_CAN_STATE_ERRORPASSIVE: + { + state = NRF_SCAN_STATE_ERROR_PASSIVE; + } break; + case NRF_CAN_STATE_ERRORWARNING: + { + state = NRF_SCAN_STATE_ERROR_WARNING; + } break; + case NRF_CAN_STATE_STOPPED: + { + state = NRF_SCAN_STATE_STOPPED; + } break; + case NRF_CAN_STATE_BUSOFF: + { + state = NRF_SCAN_STATE_BUS_OFF; + } break; + default: + { + state = NRF_SCAN_STATE_ERROR_ACTIVE; + } break; + } + + return state; +} + +nrf_scan_status_t nrf_scan_get_status(nrf_scan_t const * p_scan) +{ + NRFX_ASSERT(p_scan); + nrf_scan_status_t status; + status.state = nrf_scan_status_to_state(p_scan); + status.error = nrf_scan_status_to_err(p_scan); + return status; +} + +void nrf_scan_irq_handler(void) +{ + if (nrf_vpr_event_check(NRF_VPR, offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[SP_VPR_EVENT_IDX]))) + { + nrf_vpr_event_clear(NRF_VPR, offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[SP_VPR_EVENT_IDX])); + + can_control_block_t * p_cb = &m_cb[m_current_request.drv_inst_idx]; + + // Check for TX completion event + if (nrf_can_event_check(p_cb->p_hw_instance, NRF_CAN_EVENT_TXCOMPLETE)) + { + nrf_can_event_clear(p_cb->p_hw_instance, NRF_CAN_EVENT_TXCOMPLETE); + + if ((p_cb->prepared_pending == true) && (p_cb->transfer_in_progress == true)) // There was an ongoing transfer and we have one on hold. + { + p_cb->prepared_pending = false; + } + else + { + p_cb->transfer_in_progress = false; + } + + p_cb->evt = NRF_SCAN_EVT_TX_COMPLETE; + p_cb->handler(&p_cb->evt, p_cb->p_context); + } + + // Check for RX completion event + if (nrf_can_event_check(p_cb->p_hw_instance, NRF_CAN_EVENT_RXCOMPLETE)) + { + nrf_can_event_clear(p_cb->p_hw_instance, NRF_CAN_EVENT_RXCOMPLETE); + + for (uint8_t i = 0; i < NRF_SCAN_RXFILTER_MAX_BUFFER_SIZE; i++) + { + //get matched element index that is not in any mailbox + bool filter_matched = + nrf_can_rxfilter_filtermatched_get((NRF_CAN_Type *)p_cb->p_hw_instance, i); + bool in_mailbox = + nrf_can_rxfilter_inmailbox_get((NRF_SP_CAN_Type *)p_cb->p_hw_instance, i); + if (filter_matched && !in_mailbox) + { + memset(&(m_scan_rx_mailbox[i].rx_frame), 0, + sizeof(m_scan_rx_mailbox[i].rx_frame)); + nrf_can_frame_t tmp; + nrf_can_rxframe_get(p_cb->p_hw_instance, i, &tmp); + m_scan_rx_mailbox[i].rx_frame.identifier = tmp.identifier; + m_scan_rx_mailbox[i].rx_frame.ide = tmp.extended_format; + m_scan_rx_mailbox[i].rx_frame.rtr = tmp.remote_request; + m_scan_rx_mailbox[i].rx_frame.data_length = tmp.length; + memcpy(m_scan_rx_mailbox[i].rx_frame.data, tmp.data, tmp.length); + m_scan_rx_mailbox[i].ready = true; + + // mark as in mailbox + nrf_can_rxfilter_inmailbox_set((NRF_SP_CAN_Type *)p_cb->p_hw_instance, i, 1); + // set context to index global variable + nrf_scan_context_t * cntxt; + cntxt = (nrf_scan_context_t *)(p_cb->p_context); + cntxt->last_updated_mailbox = i; + //Clear filter matched bit to allow overriding, use nrf_scan_unlock_rx_mailbox + } + } + + p_cb->evt = NRF_SCAN_EVT_RX_COMPLETE; + p_cb->handler(&p_cb->evt, p_cb->p_context); + } + + if (nrf_can_event_check(p_cb->p_hw_instance, NRF_CAN_EVENT_ERRORDETECTED)) + { + nrf_can_event_clear(p_cb->p_hw_instance, NRF_CAN_EVENT_ERRORDETECTED); + + p_cb->evt = NRF_SCAN_EVT_ERROR; + + p_cb->handler(&p_cb->evt, p_cb->p_context); + } + + if (nrf_can_event_check(p_cb->p_hw_instance, NRF_CAN_EVENT_STATECHANGED)) + { + nrf_can_event_clear(p_cb->p_hw_instance, NRF_CAN_EVENT_STATECHANGED); + + p_cb->evt = NRF_SCAN_EVT_STATE_CHANGED; + + p_cb->handler(&p_cb->evt, p_cb->p_context); + } + } +} + +#endif // NRFX_CHECK(NRF_SCAN_ENABLED)