mips.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors.  Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 11:26:10  November 08, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		mips_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE Auto
set_global_assignment -name TOP_LEVEL_ENTITY mips32
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "04:45:01  FEBRUARY 26, 2020"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name SEARCH_PATH hw2/ -tag from_archive
set_global_assignment -name SEARCH_PATH quartus/bin64/ -tag from_archive
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SEARCH_PATH hw4/ -tag from_archive
set_global_assignment -name VERILOG_FILE source_files/xor_2.v
set_global_assignment -name VERILOG_FILE source_files/shifter.v
set_global_assignment -name VERILOG_FILE source_files/pc.v
set_global_assignment -name VERILOG_FILE source_files/mux_testbench.v
set_global_assignment -name VERILOG_FILE source_files/mux_8x1.v
set_global_assignment -name VERILOG_FILE source_files/mux_4x1_32.v
set_global_assignment -name VERILOG_FILE source_files/mux_4x1.v
set_global_assignment -name VERILOG_FILE source_files/mux_2x1_32.v
set_global_assignment -name VERILOG_FILE source_files/mux_2x1_13.v
set_global_assignment -name VERILOG_FILE source_files/mux_2x1_5bit.v
set_global_assignment -name VERILOG_FILE source_files/mux_2x1.v
set_global_assignment -name VERILOG_FILE source_files/msb_alu_1.v
set_global_assignment -name VERILOG_FILE source_files/mips32.v
set_global_assignment -name VERILOG_FILE source_files/mips_registers.v
set_global_assignment -name VERILOG_FILE source_files/mips_memory.v
set_global_assignment -name VERILOG_FILE source_files/instruction_memory.v
set_global_assignment -name VERILOG_FILE source_files/full_adder.v
set_global_assignment -name VERILOG_FILE source_files/extend.v
set_global_assignment -name VERILOG_FILE source_files/control_unit.v
set_global_assignment -name VERILOG_FILE source_files/concat.v
set_global_assignment -name VERILOG_FILE source_files/alu_testbench.v
set_global_assignment -name VERILOG_FILE source_files/alu_32_testbench.v
set_global_assignment -name VERILOG_FILE source_files/alu_32.v
set_global_assignment -name VERILOG_FILE source_files/alu_1.v
set_global_assignment -name VERILOG_FILE source_files/adder_32.v
set_global_assignment -name VERILOG_FILE source_files/adder_13.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top