computer_structure_experiment_f4_a/alu.vhd at main · wang-kaopu/computer_structure_experiment_f4_a · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all; -- 使用numeric_std库以支持算术运算

entity alu is                           -----实体声明外部接口
    port (
        op: in STD_LOGIC_VECTOR(2 downto 0);   --选择控制运算类型
        accD: in STD_LOGIC_VECTOR(7 downto 0); -- 累加器的8位数据
        dBus: in STD_LOGIC_VECTOR(7 downto 0); -- 数据总线用于运算
        result: out STD_LOGIC_VECTOR(7 downto 0);   --结果的输出
        accZ: out STD_LOGIC
);
end alu;

--architecture aluArch of alu is
--	    signal tempResult : STD_LOGIC_VECTOR(15 downto 0); -- 用于存储乘法结果的中间信号
--begin
--	    -- 计算乘法结果
--    tempResult <= accD * dBus when op = "010" else
----                  accD * (not dBus) when op = "0111" else
--                  (others => '0');
--	  result <=
----				(not accD) + "00000001" when op ="0000" else
----			 accD + dBus when op ="0001" else
--			 accD + dBus when op ="000" else
----			 accD+"10000000" when op="0010" else
----			 dBus+"10000000" when op="0011" else
----			 (not accD)-"00000001" when op="0100" else
----			 accD-dBus when op="0101" else
--			 accD-dBus when op="001" else
----			 tempResult(7 downto 0) when op="0110" or op = "0111" else
--			 tempResult(7 downto 0) when op="010" else
--
--			 accD AND  dBus when op="1010" else
--			 accD NAND dBus when op="1011" else
--			 accD OR   dBus when op="1100" else
--			 accD NOR  dBus when op="1101" else
--			 accD XNOR dBus when op="1110" else
--			 NOT accD when op="1111" else
--			 "00000000";
--	 accZ <= not (accD(0) or  accD(1) or  accD(2) or  accD(3) or
--				 accD(4) or  accD(5) or  accD(6) or  accD(7)
--);
--end aluArch;

architecture aluArch of alu is
    signal tempResult : unsigned(15 downto 0); -- 用于存储乘法结果的中间信号
    signal tempDivResult : signed(7 downto 0); -- 用于存储除法结果的中间信号
begin
    -- 计算乘法结果
    tempResult <= unsigned(accD) * unsigned(dBus) when op = "010" else
                  (others => '0'); -- 默认值，避免未定义行为

    -- 计算除法结果
    tempDivResult <= signed(accD) / signed(dBus) when op = "011" else
                    (others => '0'); -- 默认值，避免未定义行为

    -- 条件信号赋值
    result <= std_logic_vector(unsigned(accD) + unsigned(dBus)) when op = "000" else -- 加法
              std_logic_vector(unsigned(accD) - unsigned(dBus)) when op = "001" else -- 减法
              std_logic_vector(tempResult(7 downto 0)) when op = "010" else -- 乘法
              std_logic_vector(unsigned(tempDivResult)) when op = "011" else -- 除法
              (not accD) + "00000001" when op = "100" else -- 求补
              accD AND dBus when op = "101" else -- 与
              accD OR dBus when op = "110" else -- 或
              NOT accD when op = "111" else -- 取反
              "00000000"; -- 默认值

    -- 计算accZ
    accZ <= not (accD(0) or accD(1) or accD(2) or accD(3) or
                 accD(4) or accD(5) or accD(6) or accD(7));
end aluArch;