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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

ci(perf-trigger): refactor & support spec17/26 module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. topic: performance To improve performance
#6077 opened Jun 9, 2026 by ngc7331 Member • Draft
1 task
2
timing(CommonHR): fix CommonHR timing in s3 module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: timing To fix bad timing
#6076 opened Jun 9, 2026 by sleep-zzz Contributor • Draft
1
fix(mnret): fix MNret error and clear mnstatus.mnpv/mnpp module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6075 opened Jun 9, 2026 by sinceforYy Contributor Loading…
submodule: bump XSCache module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6072 opened Jun 8, 2026 by ywlcode Contributor Loading…
1
fix(csr, xstatus): mark HLV/HLVX/HSV memory traps as virtual module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6071 opened Jun 8, 2026 by wissygh Contributor • Draft
1
fix(rob): fix the X-state propagation for commit_w module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6070 opened Jun 8, 2026 by xiaofeibao-xjtu Contributor Loading…
submodule(CoupledL2): bump CoupledL2
#6069 opened Jun 8, 2026 by yulightenyu Contributor Loading…
fix(CSR, vscause): gate VS hvictl interrupt cause by interrupt type module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6067 opened Jun 8, 2026 by wissygh Contributor • Draft
1
fix(mtval2): fix the incorrect generation of mtval2 during IGPF module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6058 opened Jun 5, 2026 by sinceforYy Contributor Loading…
fix(satp): fix old satp/vsatp to update xpec and xtval module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6056 opened Jun 5, 2026 by sinceforYy Contributor Loading…
feat(MMU): do not cache pageFault pte entries in TLB module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs
#6053 opened Jun 3, 2026 by good-circle Contributor Loading…
4
fix(PMA,PMP): fix RMW base value for CSRRS/CSRRC in PMP and PMA module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6052 opened Jun 3, 2026 by sinceforYy Contributor • Draft
1
fix(PMA,PMP): fix RMW base value for CSRRS/CSRRC in PMP and PMA module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6051 opened Jun 3, 2026 by sinceforYy Contributor Loading…
timing(ibuffer): optimize ibuffer bypass logic to improve timing module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#6047 opened Jun 1, 2026 by my-mayfly Collaborator Loading…
1
feat(CSR): make commit stuck critical error check configurable v3 module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: top XSTop, XSTile, XSParameters, configs
#6046 opened Jun 1, 2026 by HeiHuDie Collaborator Loading…
1
timing(ICache): disable EnableWayLookupBypass by default module: frontend Bpu, Ftq, Ifu, ICache, IBuffer note: do not squash (PR) For maintainer: please use rebase-and-merge instead of squash-and-merge topic: timing To fix bad timing
#6044 opened May 29, 2026 by ngc7331 Member • Draft
fix(vstopi): fix vstopi Candidate3 enable conditation module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan
#6031 opened May 27, 2026 by sinceforYy Contributor Loading…
fix(RVH): check HLVX final physical execute permission module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6017 opened May 25, 2026 by fuhuakai Loading…
fix(RVH): check HLVX final physical execute permission module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6016 opened May 25, 2026 by fuhuakai Loading…
1
fix(csr): fix the update logic of xepc module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6014 opened May 25, 2026 by sinceforYy Contributor • Draft
refactor(bpu/replacer): unify ReplacerState porting module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: code quality To make code more readable & maintainable
#6008 opened May 22, 2026 by ngc7331 Member Loading…
3
feat(mbtb): parameterize EnableTargetFix module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#6007 opened May 22, 2026 by ngc7331 Member Loading…
1
feat(dcache): add one more dcache node module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#6005 opened May 22, 2026 by Ruomio Contributor • Draft
timing(sc): move non-bias SC percsum accumulation from s1 to s2 module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: timing To fix bad timing
#5999 opened May 21, 2026 by sleep-zzz Contributor Loading…
2
feat(Frontend): implement 2-fetch module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5996 opened May 21, 2026 by TheKiteRunner24 Collaborator Loading…
6
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