nrfconnect · eivindj-nordic · Feb 24, 2026 · Jan 7, 2026
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+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
+zephyr_library_sources(init.c)
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+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+config BOARD_BM_NRF54LV10DK
+	select BOARD_LATE_INIT_HOOK
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+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+config BOARD_BM_NRF54LV10DK
+	select SOC_NRF54LV10A_ENGA_CPUAPP if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE || \
+					     BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT || \
+					     BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE || \
+					     BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
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+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+choice NRF_GRTC_TIMER_SOURCE
+	default NRF_GRTC_TIMER_SOURCE_LFLPRC if !$(dt_nodelabel_enabled,lfxo)
+endchoice
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+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+config PARTITION_MANAGER
+	default n
+
+if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE || \
+	BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT
+
+choice SOFTDEVICE_SELECTION
+	default SOFTDEVICE_S115
+endchoice
+
+endif # BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE || \
+	# BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT
+
+if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE || \
+	BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
+
+choice SOFTDEVICE_SELECTION
+	default SOFTDEVICE_S145
+endchoice
+
+endif # BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE || \
+	# BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
+
+
+# Kconfigs for all MCUboot board variants
+if BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT || \
+	BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
+
+choice BM_BOOTLOADER
+	default BM_BOOTLOADER_MCUBOOT
+endchoice
+
+choice BM_BOOTLOADER_MCUBOOT_SIGNATURE_TYPE
+	default BM_BOOTLOADER_MCUBOOT_SIGNATURE_TYPE_ED25519
+endchoice
+
+config BM_BOOTLOADER_MCUBOOT_SIGNATURE_USING_KMU
+	default y
+
+choice BM_BOOTLOADER_MCUBOOT_IMG_HASH_ALG
+	default BM_BOOT_IMG_HASH_ALG_PURE
+endchoice
+
+choice BM_FIRMWARE_LOADER
+	default BM_FIRMWARE_LOADER_BT_MCUMGR
+endchoice
+
+config BM_BOOTLOADER_MCUBOOT_FIRMWARE_LOADER_ENTRANCE_BOOT_MODE
+	default y
+
+endif # BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S115_SOFTDEVICE_MCUBOOT ||
+	# BOARD_BM_NRF54LV10DK_NRF54LV10A_CPUAPP_S145_SOFTDEVICE_MCUBOOT
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+/*
+ * Copyright (c) 2026 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/* Override NCS default. */
+#include "bm_nrf54lv10dk_nrf54lv10a_peripherals.dtsi"
+#include "bm_nrf54lv10dk_nrf54lv10a_oscillator.dtsi"
+
+/delete-node/ &cpuapp_sram;
+
+/ {
+	compatible = "nordic,bm_nrf54lv10dk_nrf54lv10a-cpuapp";
+	model = "Nordic Bare Metal nRF54LV10 DK nRF54LV10 Application MCU";
+
+	chosen {
+		zephyr,flash-controller = &rram_controller;
+		zephyr,boot-mode = &boot_mode0;
+	};
+
+	soc {
+		cpuapp_sram: memory@20000080 {
+			compatible = "mmio-sram";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* Size reduced by 0x80 bytes to account for the start address offset.
+			 * As total size of SRAM is not 1kB aligned,
+			 * 0x140 bytes are added to the 191 kB.
+			 */
+			reg = <0x20000080 (DT_SIZE_K(191) - 0x80 + 0x140)>;
+			ranges = <0x0 0x20000080 (DT_SIZE_K(191) - 0x80 + 0x140)>;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		nrf_kmu_reserved_push_area: memory@20000000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x20000000 0x80>;
+			zephyr,memory-region = "nrf_kmu_reserved_push_area";
+		};
+	};
+};
+
+/* Override NCS default to use entire RRAM for application CPU. */
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1012)>;
+};
+
+&gpregret1 {
+	status = "okay";
+
+	boot_mode0: boot_mode@0 {
+		compatible = "zephyr,retention";
+		status = "okay";
+		reg = <0x0 0x1>;
+	};
+};
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+/*
+ * Copyright (c) 2026 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54lv10a_enga_cpuapp.dtsi>
+#include "bm_nrf54lv10dk_nrf54lv10a_cpuapp_common.dtsi"
+
+/ {
+	chosen {
+		zephyr,flash = &cpuapp_rram;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &app_ram;
+	};
+};
+
+&cpuapp_rram {
+	status = "okay";
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: partition@0 {
+			label = "slot0";
+			reg = <0x00000000 DT_SIZE_K(896)>;
+		};
+
+		storage_partition: partition@e0000 {
+			compatible = "fixed-subpartitions";
+			label = "storage";
+			reg = <0x000e0000 DT_SIZE_K(8)>;
+			ranges = <0x0 0xe0000 DT_SIZE_K(8)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			peer_manager_partition: partition@0 {
+				label = "peer_manager";
+				reg = <0x00000000 DT_SIZE_K(4)>;
+			};
+
+			storage0_partition: partition@1000 {
+				label = "storage0";
+				reg = <0x00001000 DT_SIZE_K(4)>;
+			};
+		};
+
+		softdevice_partition: partition@e2000 {
+			label = "softdevice";
+			reg = <0x000e2000 DT_SIZE_K(107)>;
+		};
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+
+	softdevice_static_ram: sram@0 {
+		label = "softdevice_static_ram";
+		reg = <0x0 0x1380>;
+	};
+
+	softdevice_dynamic_ram: sram@1380 {
+		label = "softdevice_dynamic_ram";
+		reg = <0x1380 DT_SIZE_K(12)>;
+	};
+
+	app_ram: sram@4380 {
+		label = "app_ram";
+		reg = <0x4380 (DT_SIZE_K(174) + 0x140)>;
+	};
+};
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+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+identifier: bm_nrf54lv10dk/nrf54lv10a/cpuapp/s115_softdevice
+name: Bare_Metal-nRF54LV10-DK-nRF54LV10A-Application-S115-SoftDevice
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - xtools
+  - zephyr
+sysbuild: true
+ram: 174
+flash: 896
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+#
+# Copyright (c) 2026 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_BM_UARTE_CONSOLE=y
+
+# Remove boot banner
+CONFIG_NCS_BOOT_BANNER=n
+CONFIG_BOOT_BANNER=n
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# MPU-based null-pointer dereferencing detection cannot
+# be applied as the (0x0 - 0x400) is unmapped for this target.
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable Cache
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_EXTERNAL_CACHE=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable partition manager
+CONFIG_PARTITION_MANAGER_ENABLED=n
+
+# Disable multithreading
+CONFIG_MULTITHREADING=n
+CONFIG_ZERO_LATENCY_IRQS=y
+
+# Disable generation of the redundant SW ISR table
+CONFIG_GEN_SW_ISR_TABLE=n
+
+# Allow FLASH writes
+CONFIG_MPU_ALLOW_FLASH_WRITE=y
+
+# Shrink
+CONFIG_GPIO=n
+
+# Enable all NRFX drivers
+CONFIG_NRFX_CLOCK=y
+CONFIG_NRFX_CLOCK_LFXO_TWO_STAGE_ENABLED=y
+CONFIG_NRFX_COMP=y
+CONFIG_NRFX_LPCOMP=y
+CONFIG_NRFX_EGU10=y
+CONFIG_NRFX_EGU20=y
+CONFIG_NRFX_GPIOTE20=y
+CONFIG_NRFX_GPIOTE30=y
+CONFIG_NRFX_GPPI=y
+CONFIG_NRFX_GRTC=y
+CONFIG_NRFX_POWER=y
+CONFIG_NRFX_RRAMC=y
+CONFIG_NRFX_SAADC=y
+CONFIG_NRFX_SPIM=y
+CONFIG_NRFX_SPIS=y
+CONFIG_NRFX_SYSTICK=y
+CONFIG_NRFX_TEMP=y
+CONFIG_NRFX_TIMER=y
+CONFIG_NRFX_TWIM=y
+CONFIG_NRFX_UARTE=y
+CONFIG_NRFX_WDT=y
+CONFIG_NRFX_PRS_BOX_0=y
+CONFIG_NRFX_PRS_BOX_1=y
+CONFIG_NRFX_PRS_BOX_2=y
+CONFIG_NRFX_PRS_BOX_3=y